ADSP-SC57xSHARC双核处理器解决方案(特性,框图,电路图).doc
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1、ADSPSC57xSHARC双核处理器解决方案(特性,框图,电路图)ADI公司的ADSP-SC57x/2157x系列处理器集成了两个增强型SHARC+内核和先进的DSP加速器(FIR,IIR),功耗低于2W,功效比以前的SHARC产品高5倍以上,专为需要DSP协处理器并包括两个SHARC+内核和一个匹配DSP内核的外设集的应用而设计,主要用在汽车,消费电子和专业音频,多轴电机控制和能源分配系统.本文介绍了ADSP-SC57x/ADSP-2157x系统特性,处理器框图,ARM Cortex-A5处理器器框图,SHARC处理器框图,SHARC+SIMD处理器核框图以及评估板ADSP-SC573 E
2、Z-KIT主要特性,框图,电路图和材料清单.The ADSP-SC57x/ADSP-2157x processors are members of theSHARC family of products. The ADSP-SC57x processor isbased on the SHARC+ dual-core and the ARM Cortex-A5core. The ADSP-SC57x/ADSP-2157x SHARC processors aremembers of the single-instrucTIon, mulTIple data (SIMD)SHARC family
3、 of digital signal processors (DSPs) that featureAnalog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floaTIng-point processors are opTImized for high performanceaudio/floating-point applications with large on-chipstatic random-access memory (SRAM), multiple internal busesthat elimi
4、nate input/output (I/O) bottlenecks, and innovativedigital audio interfaces (DAI). New additions to the SHARC+core include cache enhancements and branch prediction, whilemaintaining instruction set compatibility to previous SHARC products.By integrating a set of industry leading system peripherals a
5、ndmemory, the ARM Cortex-A5 and SHARC processor is the platform of choice for applicationsthat require programmability similar to reducedinstruction set computing (RISC), multimedia support, andleading edge signal processing in one integrated package. Theseapplications span a wide array of markets,
6、including automotive,professional audio, and industrial-based applications thatrequire high floating-point performance.ADSP-SC57x/ADSP-2157x系统特性:Dual-enhanced SHARC+ high performance floating-pointcoresUp to 450 MHz per SHARC+ coreUp to 3 Mb (384 kB) L1 SRAM memory per core with parity(optional abil
7、ity to configure as cache)32-bit, 40-bit, and 64-bit floating-point support32-bit fixed pointByte, short word, word, long word addressedARM Cortex-A5 core450 MHz/720 DMIPS with NEON/VFPv4-D16/Jazelle32 kB L1 instruction cache with parity/32 kB L1 data cachewith parity256 kB L2 cache with parityPower
8、ful DMA systemOn-chip memory protection图1.ADSP-SC57x/ADSP-2157x处理器框图图2.ADSP-SC57x/ADSP-2157xARM Cortex-A5处理器器框图图3.SHARC处理器框图图4.SHARC+SIMD处理器核框图评估板ADSP-SC573 EZ-KITThank you for purchasing the Analog Devices, Inc. ADSP-SC573 EZ-KITevaluation system.The ADSP-SC573 processor is a members of the SHARC f
9、amily of products. The ADSP-SC573 processor isbased on the SHARC+ dual-core and the ARM Cortex-A5TM core. The ADSP-SC573SHARC processor is amembers of the SIMD SHARC family of DSPs that feature Analog Devices Super Harvard Architecture. These 32-bit/40- bit/64-bit floating-point processors are optim
10、ized for high performance audio/floating-point applicationswith their large onchip SRAM, multiple internal buses to eliminate I/O bottlenecks, and innovative digital audiointerfaces (DAI). New enhancements to the SHARC+ core add cache enhancements, branch prediction, and otherinstruction set improve
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