Xilinx FPGA中SRL原理.doc
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1、Xilinx FPGA中SRL原理SRL(移位寄存器)资源,在FPGA中都有,不过是叫不同的名字。Xilinx FPGA内部的LUT有个特殊功能,就是可以配置成可变长度SRL。5输入的一个LUT可以变成32bit 的SRL6输入的,可以变成64bit的SRL所以,你写的SRL可能被综合成LUT。可以定义移位长度的移位寄存器。就是用一个lut可以实现16位的移位寄存器。SRL16 的是 16bit移位寄存器查找表 / 16-Bit Shift Register Look-Up-Table (LUT)在一个LUT中可以实现16个FF移位的功能!SSRL16 SRL16_inst (.Q(Q), /
2、 SRL data output.A0(A0), / Select0 input.A1(A1), / Select1 input.A2(A2), / Select2 input.A3(A3), / Select3 input.CLK(CLK), / Clock input.D(D) / SRL data input);Xilinx 官网的说明原理SRL16 is a shift register look up table (LUT)。 The inputs A3, A2, A1, and A0 select the output length of the shift register. T
3、he shift register may be of a fixed, staTIc length or it may be dynamically adjusted.The shift register LUT contents are iniTIalized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not
4、specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuraTIon.The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transiTIon. During subsequent Low-to-High clock transitions data is shifted to the
5、next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached.这里说了几点,- 移位寄存器的初始值可以用INIT属性初始化;- 移位寄存器的长度由地址线的取值决定;- 移位数据从D端输入,Q端输出- 先移入的数据是MSBXilinx 官网的说明Static Length ModeTo get a fixed length shift regist
6、er, drive the A3 through A0 inputs with static values. The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula:Length = (8*A3) +(4*A2) + (2*A1) + A0 +1If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are all ones
7、 (1111), it is 16 bits long.Xilinx 官网的说明Dynamic Length ModeThe length of the shift register can be changed dynamically by changing the values driving the A3 through A0 inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), the length of the shift r
8、egister changes from 16 bits to 8 bits.Internally, the length of the shift register is always 16 bits and the input lines A3 through A0 select which of the 16 bits reach the output.Inputs OutputAm CLK D QAm X X Q(Am)Am D Q(Am-1)m= 0, 1, 2, 3这里提示了几个要点:- 移位寄存器是可变长度的- 长度的改变由地址线来指定- 内部的寄存器长度是不变的,只是截取的长度
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