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1、中英文资料中英文资料 DS18B20 Programmable Resolution 1-Wire Digital Thermometer FEATURES _Unique 1-WireTM interface requires only oneport pin for communication _.Multidrop capability simplifies distributedtemperature sensing applications _ Requires no external components _ Can be powered from data line. Power
2、 supply range is 3.0V to 5.5V _ Zero standby power required _ Measures temperatures from -55C to +125C. Fahrenheit equivalent is -67F to +257F _ 0.5C accuracy from -10C to +85C _ Thermometer resolution is programmable from 9 to 12 bits _ Converts 12-bit temperature to digital word in 750 ms (max.) _
3、 User-definable, nonvolatile temperature alarm settings _ Alarm search command identifies and addresses devices whose temperature is outside of programmed limits (temperature alarm condition) _ Applications include thermostatic controls, industrial systems, consumer products, thermometers, or any th
4、ermally sensitive system PIN DESCRIPTION GND - Ground DQ - Data In/Out VDD - Power Supply Voltage NC - No Connect DESCRIPTION The DS18B20 Digital Thermometer provides 9 to 12-bit (configurable) temperature readings which indicate the temperature of the device. Information is sent to/from the DS18B20
5、 over a 1-Wire interface, so that only one wire (and ground) needs to be connected from a central microprocessor to a DS18B20. Power for reading, writing, and performing temperature conversions can be derived from the data line itself with no need for an external power source. Because each DS18B20 c
6、ontains a unique silicon serial number, multiple DS18B20s can exist on the same 1-Wire bus. This allows for placing temperature sensors in many different places. Applications where this feature is useful include HVAC environmental controls, sensing temperatures inside buildings, equipment or machine
7、ry, and process monitoring and control. DETAILED PIN DESCRIPTION Table 1 DS18B20Z (8-pin SOIC) and DS18P20P (TSOC): All pins not specified in this table are not to be connected. OVERVIEW The block diagram of Figure 1 shows the major components of the DS18B20. The DS18B20 has four main data component
8、s: 1) 64-bit lasered ROM, 2) temperature sensor, 3) nonvolatile temperature alarm triggers TH and TL, and 4) a configuration register. The device derives its power from the 1-Wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and co
9、ntinues to operate off this power source during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply. As an alternative, the DS18B20 may also be powered from an external 3V - 5.5V supply. Communication to the DS18B20 is via a 1-Wire port. With the 1-Wir
10、e port, the memory and control functions will not be available before the ROM function protocol has been established. The master must first provide one of five ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. These commands operate on the 64-bit laser
11、ed ROM portion of each device and can single out a specific device if many are present on the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. After a ROM function sequence has been successfully executed, the memory and control functions are accessibl
12、e and the master may then provide any one of the six memory and control function commands. One control function command instructs the DS18B20 to perform a temperature measurement. The result of this measurement will be placed in the DS18B20s scratch-pad memory, and may be read by issuing a memory fu
13、nction command which reads the contents of the scratchpad memory. The temperature alarm triggers TH and TL consist of 1 byte EEPROM each. If the alarm search command is not applied to the DS18B20, these registers may be used as general purpose user memory. The scratchpad also contains a configuratio
14、n byte to set the desired resolution of the temperature to digital conversion. Writing TH, TL, and the configuration byte is done using a memory function command. Read access to these registers is through the scratchpad. All data is read and written least significant bit first. DS18B20 3 of 26 DS18B
15、20 BLOCK DIAGRAM Figure 1 PARASITE POWER The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power whenever the DQ or VDD pins are high. DQ will provide sufficient power as long as the specified timing and voltage requirements are met (see the section titled “1
16、-Wire Bus System”). The advantages of parasite power are twofold: 1) by parasiting off this pin, no local power source is needed for remote sensing of temperature, and 2) the ROM may be read in absence of normal power. In order for the DS18B20 to be able to perform accurate temperature conversions,
17、sufficient power must be provided over the DQ line when a temperature conversion is taking place. Since the operating current of the DS18B20 is up to 1.5 mA, the DQ line will not have sufficient drive due to the 5k pullup resistor. This problem is particularly acute if several DS18B20s are on the sa
18、me DQ and attempting to convert simultaneously. There are two ways to assure that the DS18B20 has sufficient supply current during its active conversion cycle. The first is to provide a strong pullup on the DQ line whenever temperature conversions or copies to the E2 memory are taking place. This ma
19、y be accomplished by using a MOSFET to pull the DQ line directly to the power supply as shown in Figure 2. The DQ line must be switched over to the strong pullup within 10 s maximum after issuing any protocol that involves copying to the E2 memory or initiates temperature conversions. This allows ot
20、her data traffic on the 1-Wire bus during the conversion time. In addition, any number of DS18B20s may be placed on the 1-Wire bus, and if they all use external power, they may all simultaneously perform temperature conversions by issuing the Skip ROM command and then issuing the Convert T command.
21、Note that as long as the external power supply is active, the GND pin may not be floating. The use of parasite power is not recommended above 100C, since it may not be able to sustain communications given the higher leakage currents the DS18B20 exhibits at these temperatures. For applications in whi
22、ch such temperatures are likely, it is strongly recommended that VDD be applied to the DS18B20. For situations where the bus master does not know whether the DS18B20s on the bus are parasite powered or supplied with external VDD, a provision is made in the DS18B20 to signal the power supply scheme u
23、sed. The bus master can determine if any DS18B20s are on the bus which require the strong pullup by sending a Skip ROM protocol, then issuing the read power supply command. After this command is issued, the master then issues read time slots. The DS18B20 will send back “0” on the 1- Wire bus if it i
24、s parasite powered; it will send back a “1” if it is powered from the VDD pin. If the master receives a “0,” it knows that it must supply the strong pullup on the DQ line during temperature conversions. See “Memory Command Functions” section for more detail on this command protocol. STRONG PULLUP FO
25、R SUPPLYING DS18B20 DURING TEMPERATURE CONVERSION Figure 2 USING VDD TO SUPPLY TEMPERATURE CONVERSION CURRENT Figure 3 OPERATION - MEASURING TEMPERATURE The core functionality of the DS18B20 is its direct-to-digital temperature sensor. The resolution of the DS18B20 is configurable (9, 10, 11, or 12
26、bits), with 12-bit readings the factory default state. This equates to a temperature resolution of 0.5C, 0.25C, 0.125C, or 0.0625C. Following the issuance of the Convert T 44h command, a temperature conversion is performed and the thermal data is stored in the scratchpad memory in a 16-bit, sign-ext
27、ended twos complement format. The temperature information can be retrieved over the 1-Wire interface by issuing a Read Scratchpad BEh command once the conversion has been performed. The data is transferred over the 1-Wire bus, LSB first. The MSB of the temperature register contains the “sign” (S) bi
28、t, denoting whether the temperature is positive or negative. Table 2 describes the exact relationship of output data to measured temperature. The table assumes 12-bit resolution. If the DS18B20 is configured for a lower resolution, insignificant bits will contain zeros. For Fahrenheit usage, a looku
29、p table or conversion routine must be used. Temperature/Data Relationships Table 2 Configuration Register The fifth byte of the scratchpad memory is the configuration register. It contains information which will be used by the device to determine the resolution of the temperature to digital conversi
30、on. The bits are organized as shown in Figure 7. DS18B20 CONFIGURATION REGISTER Figure 7 Bits 0-4 are dont cares on a write but will always read out “1”. Bit 7 is a dont care on a write but will always read out “0”. R0, R1: Thermometer resolution bits. Table 3 below defines the resolution of the dig
31、ital thermometer, based on the settings of these two bits. There is a direct tradeoff between resolution and conversion time, as depicted in the AC Electrical Characteristics. The factory default of these EEPROM bits is R0=1 and R1=1 (12-bit conversions). Thermometer Resolution Configuration Table 3
32、 DS18B20 MEMORY MAP Figure 8 1-WIRE BUS SYSTEM The 1-Wire bus is a system which has a single bus master and one or more slaves. The DS18B20 behaves as a slave. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (sign
33、al types and timing). HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or 3-state outputs. The 1-Wire po
34、rt of the DS18B20 (DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus requires a pullup resistor of approximately 5k. The idle state for the 1-Wire bus is high. If for any reason
35、a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire bus is in the inactive (high) state during the recovery period. If this does not occur and the bus is left low for more tha
36、n 480 s, all components on the bus will be reset. TRANSACTION SEQUENCE The protocol for accessing the DS18B20 via the 1-Wire port is as follows: _ Initialization _ ROM Function Command _ Memory Function Command _ Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initia
37、lization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS18B20 is on the bus and is ready to operate. For more details, see the “1-Wire Sign
38、aling” section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the five ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 5): Read ROM 33h This command allows the bus master to read
39、 the DS18B20s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS18B20 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wi
40、red AND result). Match ROM 55h The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS18B20 on a multidrop bus. Only the DS18B20 that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not
41、 match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. Skip ROM CCh This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If m
42、ore than one slave is present on the bus and a Read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired AND result). Search ROM F0h When a system is initially brought up, the bus
43、master might not know the number of devices on the 1- Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. Alarm Search ECh The flowchart of this command is identical to the
44、Search ROM command. However, the DS18B20 will respond to this command only if an alarm condition has been encountered at the last temperature measurement. An alarm condition is defined as a temperature higher than TH or lower than TL. The alarm condition remains set as long as the DS18B20 is powered
45、 up, or until another temperature measurement reveals a non-alarming value. For alarming, the trigger values stored in EEPROM are taken into account. If an alarm condition exists and the TH or TL settings are changed, another temperature conversion should be done to validate any alarm conditions. DS
46、18B20 12 of 26 Example of a ROM Search The ROM search process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pas
47、s, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. The following example of the ROM search process assumes four different devices are connected to the same 1-Wire bus. The ROM data of the four dev
48、ices is as shown: ROM1 00110101. ROM2 10101010. ROM3 11110101. ROM4 00010001. The search process is as follows: 1. The bus master begins the initialization sequence by issuing a reset pulse. The slave devices respond by issuing simultaneous presence pulses. 2. The bus master will then issue the Sear
49、ch ROM command on the 1-Wire bus. 3. The bus master reads a bit from the 1-Wire bus. Each device will respond by placing the value of the first bit of their respective ROM data onto the 1-Wire bus. ROM1 and ROM4 will place a 0 onto the 1-Wire bus, i.e., pull it low. ROM2 and ROM3 will place a 1 onto the 1-Wire bus by allowing the line to stay high. The result is the logical AND of all devices on the line, therefore the bus master sees a 0. The bus master reads another bit. Since the Search ROM data command is being executed, all of the devices on the 1-Wi
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