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1、BRITISH STANDARD CONFIRMED JUNE 1989 BS CECC 90000: Addendum 1: 1983 Harmonized system of quality assessment for electronic components Generic specification: Monolithic integrated circuits Addendum 1. Screening UDC 621.3.049.774 Licensed Copy: London South Bank University, London South Bank Universi
2、ty, Sat Dec 09 01:43:19 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90000:Addendum 1:1983 This British Standard, having been prepared under the direction of the Electronic Components Standards Committee, was published under the authority of the Board of BSI and comes into effect on 29 July 19
3、83 BSI 04-2000 The following BSI references relate to the work on this standard: Committee reference ECL/17 Draft for comment 80/27840 DC ISBN 0 580 13357 5 Committees responsible for this British Standard This British Standard was published under the direction of the Electronic Components Standards
4、 Committee ECL/-. Its preparation was entrusted to Technical Committee ECL/17 upon which the following bodies were represented: British Broadcasting Corporation British Telecom Business Equipment Trade Association Electronic Components Industry Federation Electronic Engineering Association Ministry
5、of Defence National Supervising Inspectorate Society of British Aerospace Companies Limited Telecommunication Engineering this exclusion shall not apply. Current density shall be determined by design not visual inspection. 4) Scratch in the metallization over a passivation step that leaves less than
6、 75 % of the original metal width at the step undisturbed NOTERequirements of A.3.3.1.1 1) to 4) can be excluded for the last 25 % of linear length of the contact cut and all metal beyond on the termination end(s) of the metallization runs. In these cases there shall be at least a continuous 50 % of
7、 the contact opening area covered by metallization and at least a continuous 40 % of the contact opening perimeter covered by undisturbed metallization (see Figure 18). 5) Any scratch in the metallization, over the gate oxide bridge, that exposes underlying passivation and leaves less than 50 % of t
8、he length or width of the metallization between source and drain diffusions undisturbed (see Figure 19) (applicable to MOS structures) Licensed Copy: London South Bank University, London South Bank University, Sat Dec 09 01:43:19 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90000:Addendum 1:19
9、83 16 BSI 04-2000 6) A scratch in the metallization that exposes the dielectric material of a thin film capacitor or crossover 7) A scratch in the bonding pad or fillet area that exposes underlying passivation and reduces the metallization path width connecting the bond to the interconnecting metall
10、ization to less than 50 % of the narrowest entering interconnect metallization stripe width. If two or more stripes enter a bonding pad, each shall be considered separately 8) Scratches, probe mark(s) etc. in the bonding pad area that exposes underlying passivation of more than 25 % of the original
11、unglassivated metallization area. A.3.3.1.2 Metallization voids: 1) Void(s) in the metallization that leaves less than 50 % of the original metal width undisturbed (see Figure 20) NOTERequirements of A.3.3.1.2 1) can be excluded for peripheral power or ground metallization where parallel paths exist
12、 so that an opening at the void(s) would not cause an unintended isolation of the metallization path. When application of this exclusion causes or permits a device design to exceed the current density limitation imposed by the design document, this exclusion shall not apply. Current density shall be
13、 determined by design, not visual inspection. 2) Void(s) in the metallization over a passivation step that leaves less than 75 % of the original metal width at the step undisturbed NOTERequirements of A.3.3.1.2 1) and 2) can be excluded for the last 25 % of linear length of the contact cut and all m
14、etal beyond on the termination end(s) of metallization runs. In these cases there shall be at least 50 % of the contact opening area covered by metallization and at least a continuous 40 % of the contact opening perimeter covered by undisturbed metallization (see Figure 18). 3) Void(s) in the metall
15、ization over the gate oxide bridge that leaves less than 75 % of the metallization length (L) between source and drain diffusions undisturbed (see Figure 19) (applicable to MOS structures) 4) Void(s) that leaves less than 60 % of the metallization area over the gate oxide bridge undisturbed (applica
16、ble to MOS structures) 5) Void(s) that leaves less than 75 % of the metallization width coincident with the source or drain diffusion junction line, undisturbed (see Figure 19) (applicable to MOS structures) 6) Void(s) in the bonding pad area that leaves less than 75 % of its original unglassivated
17、metallization area undisturbed 7) Void(s) in the bonding pad or fillet area that reduces the metallization path width connecting the bond to the interconnecting metallization to less than 50 % of the narrowest entering interconnect metallization stripe width (see Figure 4) NOTEIf two or more stripes
18、 enter a bonding pad, each shall be considered separately. 8) Void(s) in the metallization of a thin film capacitor that reduces the metallization area by more than 25 %. A.3.3.1.3 Metallization corrosion: any metallization corrosion. A.3.3.1.4 Metallization adherence: any metallization lifting, pee
19、ling or blistering. A.3.3.1.5 Metallization probing: requirements contained in A.3.3.1.1 shall apply as limitations on probing damage. A.3.3.1.6 Metallization bridging: any metallization bridge where the separation between any two metallization paths is reduced to less than 2,5 4m unless by design.
20、A.3.3.1.7 Metallization alignment: 1) Contact window that has less than 50 % of its area covered by metallization 2) Contact window that has less than 40 % of its perimeter covered by metallization NOTEIf in accordance with the design specification, metal is completely contained in a contact window,
21、 requirements of A.3.3.1.7 2) perimeter coverage can be deleted. 3) A metallization path not intended to cover a contact window that is separated from the window by less than 2,5 4m 4) Any exposure of the gate oxide bridge from source to drain diffusions (see Figure 5) (applicable to MOS structures)
22、 5) Any exposure of the gate oxide bridge that leaves less than 75 % of the metallization coincident with the source and drain diffusion junction line undisturbed (applicable to MOS structures) 6) Gate metallization not coincident with or extending over the diffused guard ring. Licensed Copy: London
23、 South Bank University, London South Bank University, Sat Dec 09 01:43:19 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90000:Addendum 1:1983 BSI 04-200017 NOTERequirements of A.3.3.1.7 6) apply to MOS structures containing a diffused guard ring. MOS devices that do not contain a diffused guard
24、 ring shall have a gate metallization extending not less than 2,5 4m beyond the gate oxide bridge (see Figure 19 and Figure 5). A.3.3.2 Diffusion and passivation layer(s) faults (high magnification) No device shall be acceptable that exhibits the following: 1) A diffusion junction line that unintent
25、ionally crosses another diffusion junction line (see Figure 21) 2) Any isolation diffusion that is discontinuous except isolation walls around unused areas or bonding pads or any other diffused area with less than 25 % of the original diffusion width remaining 3) Either multiple lines or a complete
26、absence of passivation visible at the edge and continuing under the metallization (see Figure 22) NOTEDouble or triple lines indicate that it can have sufficient depth to penetrate down to bare silicon; however, should the absence of glassivation in the defect area or the characteristics of the glas
27、sivation present allow verification of the presence or absence of passivation by colour comparisons, respectively, then these techniques may be used. Requirements of A.3.3.2 1) can be excluded when a second passivation layer is applied in a separate operation and by a different process prior to meta
28、llization deposition. 4) An active junction not covered by passivation, unless by design. A.3.3.3 Scribing and die defects (high magnification) No device shall be acceptable that exhibits: 1) Less than 2,5 4m of passivation visible between operating metallization or bond periphery and edge of the di
29、e NOTERequirements of A.3.3.3 1) can be excluded for beam leads and peripheral metallization including bonding pads where the metallization is at the same potential as the die. 2) A chipout in the active circuit area (see Figure 23 and Figure 9) NOTERequirements of A.3.3.3 2) can be excluded for per
30、ipheral metallization, that is at the same potential as the die. In these cases there shall be at least 50 % of the peripheral metallization width undisturbed at the chipout. 3) Any substrate or passivation crack in the active circuit area or a crack that exceeds 125 4m in length (see Figure 23) 4)
31、Any crack that comes closer than 2,5 4m to any operating metallization or other active-circuit area on the die (see Figure 23) NOTERequirements of A.3.3.3 4) can be excluded for peripheral metallization that is at the same potential as the die. 5) A crack, that exceeds 25 4m in length, inside the sc
32、ribe grid or scribe line that points toward operating metallization or functional circuit elements (see Figure 23) 6) Exposed silicon extending beyond the passivation edge at the point of the beam lead exit from the die (see Figure 9) (applicable to beam lead structures) 7) A crack that comes closer
33、 than 12 4m to operating beam lead metallization (see Figure 9). A.3.3.4 Bond inspection (low magnification) This inspection is mandatory for the bond type(s) and location(s) to which they are applicable when viewed from above. NOTEA wire tell is not considered part of the bond when determining phys
34、ical bond dimensions. A.3.3.4.1 Gold ball bonds: no device shall be acceptable that exhibits: 1) Gold ball bonds on the die or package post where the ball bond diameter is less than twice or greater than six times the wire diameter 2) Gold ball bonds where the wire exit is not completely within the
35、periphery of the ball 3) Gold ball bonds where the wire centre exit is not within the boundaries of the bonding pad 4) Intermetallic formation extending radially more than 2,5 4m completely around the periphery of any gold ball bond for the portion of the gold ball bond located on metal. A.3.3.4.2 W
36、edge bonds: no device shall be acceptable that exhibits: 1) Ultrasonic wedge bonds on the die or package post that are less than 1,2 times or greater than three times the wire diameter in width, or are less than 1,5 times or greater than five times the wire diameter in length (see Figure 10) 2) Ther
37、mocompression wedge bonds on the die or package post that are less than 1,5 times or greater than three times the wire diameter in width, or are less than 1,5 times or greater than five times the wire diameter in length (see Figure 10) Licensed Copy: London South Bank University, London South Bank U
38、niversity, Sat Dec 09 01:43:19 GMT+00:00 2006, Uncontrolled Copy, (c) BSI BS CECC 90000:Addendum 1:1983 18 BSI 04-2000 3) wedge bonds at the point where metallization exits from the bonding pad that do not exhibit a line of undisturbed metal visible between the periphery of the bond and at least one
39、 side of the entering metallization stripe (see Figure 4, Figure 24 and Figure 25). NOTE 1The requirements of A.3.3.4.2 3) can be excluded when the entering metallization stripe is greater than 50 4m in width and the bond pad dimension on the entering metal stripe side is greater than 90 4m. NOTE 2T
40、he requirements of A.3.3.4.2 3) for a visual line of metal can be satisfied when an acceptable wire tail obscures the area of concern, providing the following condition exists; a bond is located more than 2,5 4m from the intersecting line of the entering metallization stripe and the bonding pad, and
41、 there is no visual evidence of disturbed pad metallization at the bond and wire fall interface. A.3.3.4.3 Tailless bonds (crescent): no device shall be acceptable that exhibits: 1) Tailless bonds on the die or package post that are less than 1,2 time or greater than five times the wire diameter in
42、width, or are less than 0,5 times or greater than three times the wire diameter in length (see Figure 10) 2) Tailless bonds where the bond impression does not cover the entire width of the wire 3) Tailless bonds at the point where metallization exits from the bonding pad that do not exhibit a line o
43、f undisturbed metal visible between the periphery of the bond and at least one side of the entering metallization stripe (see Figure 24 and Figure 25). A.3.3.4.4 General (gold ball, wedge and tailless): no device shall be acceptable that exhibits; 1) Bonds on the die where less than 50 % of the bond
44、 is within the unglassivated bonding pad area 2) Bonds on the package post that are not completely within two package post widths from the inner edge of the package post 3) Bonds placed so that the wire exiting from the bond crosses over another bond 4) Bonds placed so that the separation between bo
45、nds or the bond and operating metallization not connected to it is less than 2,5 4m 5) Wire bond tails that extend over or make contact with any metallization not covered by glassivation and not connected to the wire 6) Wire bond tails that exceed two wire diameters in length at the bonding pad or f
46、our wire diameters in length at the package post 7) Bonds where less than 50 % of the bond is located within an area that is free of die preform mounting material 8) A bond on top of another bond, bond wire tail or residual segment of lead wire. An ultrasonic wedge bond alongside a previous bond whe
47、re the observable width of the first bond is reduced less than 6 4m, is considered acceptable 9) Any evidence of repair of conductors by bridging with an addition of bonding wire or ribbon 10) Any rebonding which violates the following applicable rework limitations: no scratched, open, or discontinu
48、ous metallization; paths or conductor patterns shall be repaired by bridging with an addition of bonding wire or ribbon all rebonds shall be placed on at least 50 % undisturbed metal (excluding probe marks that do not expose oxide) and no more than one rebond attempt at any design bond location shal
49、l be permitted at any pad or post and no rebond shall touch an area of exposed oxide caused by lifted metal the total number of rebond attempts shall be limited to a maximum of 10 % of the total number of bonds in the microcircuit NOTEThe 10 % limit on rebonds may be interpreted as the nearest whole number of bonds in the microcircuit. A bond shall be defined as a wire to post or wire to pad bond (for example for a 14 lead wire-bonded package there are 28 bonds). Bond-offs required to clear the bonder after an unsuccessful first bond attempt need not be considered as rebonds
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