BS-IEC-62527-2007.pdf
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1、BRITISH STANDARD BS IEC 62527:2007 Standard for Extensions to Standard Test Interface Language (STIL) for DC Level Specification ICS 25.040.01; 35.060 ? Licensed Copy: London South Bank University, London South Bank University, Wed Jan 23 01:26:35 GMT+00:00 2008, Uncontrolled Copy, (c) BSI BS IEC 62
2、527:2007 This British Standard was published under the authority of the Standards Policy and Strategy Committee on 31 December 2007 BSI 2007 ISBN 978 0 580 59315 4 National foreword This British Standard is the UK implementation of IEC 62527:2007. The UK participation in its preparation was entruste
3、d to Technical Committee GEL/93, Design automation. A list of organizations represented on this committee can be obtained on request to its secretary. This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. Complianc
4、e with a British Standard cannot confer immunity from legal obligations. Amendments issued since publication Amd. No. DateComments Licensed Copy: London South Bank University, London South Bank University, Wed Jan 23 01:26:35 GMT+00:00 2008, Uncontrolled Copy, (c) BSI IEC 62527 Edition 1.0 2007-11 I
5、NTERNATIONAL STANDARD Standard for Extensions to Standard Test Interface Language (STIL) for DC Level Specification IEEE 1450.2 BS IEC 62527:2007 IEE 1450.2-2002 Licensed Copy: London South Bank University, London South Bank University, Wed Jan 23 01:26:35 GMT+00:00 2008, Uncontrolled Copy, (c) BSI
6、? 5 ? ? 6 ? ?7 ?7 ? ?7 ? ? ?7 ? ? ? ?10 ?! ? ?11 “?#$?% 8. Extensions to Clause 19, Spec and Selector blocks ?#?+?(,#V#%,F?8#-?W ?+?) ?$?+?%,*#?#*?,F?8#-U- ?+?)?$?+?%,?#(?,F?8#-U- X ?;?#G?(! ? Selector dc_setup; Timing slow; DCLevels slow_dc; DCSets all_sets; PatternBurst dc_patts; 9.3 DCLevels and
7、DCSets usage in PatternExec and Pattern blocks ?%*?- ?+?)?“?dc_exprU- ?X-Y ?X-Y ?) ?$G?(! ?! ?%*? IClamp iddmax; VDDA VForce vdda; IClamp iddamax; ins VIH vih1; VIL vil1; VIHSlew 1V/1ns; VILSlew 1V/1ns; outs VOH voh1; VOL vol1; IOH ioh1; IOL iol1; LoadVRef vth1; inouts VIH vih2; VIL vil2; 19 BS IEC
8、62527:2007 IEE 1450.2-2002 Licensed Copy: London South Bank University, London South Bank University, Wed Jan 23 01:26:35 GMT+00:00 2008, Uncontrolled Copy, (c) BSI VOH voh2; VOL vol2; IOH ioh2; IOL iol2; LoadVref vth2; 10.3 InheritDCLevels Processing (! ?)?! ?%*? VOL -0.3V; DCLevels loadboard Inher
9、itDCLevels ate; sig1 LoadVRef 0.2V; ResistiveTermination 50Ohm; TermVRef -2V; DCLevels dut InheritDCLevels loadboard; sig1 LoadVRef 0.4V; VOH 1.2V; ? )?! ? ?1 ?$? DCLevels switch2; 12. DCSequence block (! ?%?3? 1ms VDD+VDDA Connect Supply; 1ms VDD Apply 100mA; / Apply line charge current 100us VDD A
10、pply; / Apply voltage programmed by test 1ms VDDA Apply 50mA; / Apply line charge current 100us VDDA Apply; / Apply voltage programmed by test 1ms signals Connect Load; Connect Driver Comparator; DCSequence PowerRaise / Increasing VDD 1ms VDD Ramp 5ms; / Ramp to programmed voltage 1ms VDDA Ramp 5ms;
11、 6ms signals Apply; / Apply new values to signals after supplies change DCSequence PowerLower / Decreasing VDD 1ms signals Apply; / Apply new values to signals before supplies change 1ms VDDA Apply; / Apply voltage programmed by test 23 BS IEC 62527:2007 IEE 1450.2-2002 Licensed Copy: London South B
12、ank University, London South Bank University, Wed Jan 23 01:26:35 GMT+00:00 2008, Uncontrolled Copy, (c) BSI 1ms VDD Apply; DCSequence EndOfProgram / End of program 0s VDD+VDDA+signals Ramp 5ms 0V; / Ramp to 0V 6ms signals Disconnect Driver Comparator; Disconnect Load; 1ms VDDA+VDD Disconnect Supply
13、; 24 BS IEC 62527:2007 IEE 1450.2-2002 Licensed Copy: London South Bank University, London South Bank University, Wed Jan 23 01:26:35 GMT+00:00 2008, Uncontrolled Copy, (c) BSI ?1 ? ?1 ?! ?%?3?! ?B?1 ? ? 13. Extensions to Clause 18, WaveformTable block (! ? / define multiple drive high levels Timing
14、 slow WaveformTable wft1 Period 30ns; Waveforms mult ABCD 0ns U1; 5ns U0/U1/U2/U30; 10ns U0/U1/U2/U31; 15ns U0/U1/U2/U32; 20ns U0/U1/U2/U33; Pattern one W wft1; V mult = ADCB; Figure 5Example waveform generated by switching DC levels within a cycle ?.? ? ? ? ? (.(. DCLevels switch1; V inouts = 01010
15、1; V inouts = 101010; V inouts = 0L1HL0; DCLevels switch2; V inouts = LHLHLH; V inouts = HLHLHL; V inouts = L10H01; 28 BS IEC 62527:2007 IEE 1450.2-2002 Licensed Copy: London South Bank University, London South Bank University, Wed Jan 23 01:26:35 GMT+00:00 2008, Uncontrolled Copy, (c) BSI Annex A (
16、informative) ? (! ? Signals en_ In; clk In; d1 In; d2 In; a0 InOut; a1 InOut; a2 InOut; VDD Supply; VDDS Supply; SignalGroups ins en_+d1+d2; clks clk; inouts a0+a1+a2; all ins+clks+inouts; Spec all_specs Category all_cats per1 = 100ns; dely1 = 10ns; off1 = 25ns; off2 = 50ns; stb1 = 75ns; per2 = 50ns
17、; dely2 = 5ns; off3 = 12.5ns; off4 = 25ns; stb2 = 40ns; vdd_low = 1.5V; vdds_low = 2.7V; vdd_hi = 1.8V; vdds_hi = 3.3V; iddmax = 500mA; vih_low = 2.5V; vil_low = 0V; voh_low = 2.4V; (! ?! ? ioh_low = 1mA; iol_low = 1.5mA; vth_low = 1.4V; vih_hi = 3V; vil_hi = 0V; voh_hi = 2.9V; vol_hi = 0.5V; ioh_hi
18、 = 2mA; iol_hi = 4mA; vth_hi = 1.7V; slew = 1V/1ns; Timing slow WaveformTable ts1 Period per1; Waveforms ins LH dely1 D/U; clks LC 0ns D; off1 D/U; off2 D; inouts LH dely1 D/U; inouts 01ZM stb1 L/H/T/X; WaveformTable ts2 Period per2; Waveforms ins LH dely2 D/U; clks LC 0ns D; off3 D/U; off4 D; inout
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