ECA-EIA-ECA-469-D-2006.pdf
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1、ANSI/ElA-469-0-2006 Approved: April 6,2006 EIA STANDARD STANDARD TEST METHOD FOR DESTRUCTIVE PHYSICAL ANALYSIS (DPA) OF CERAMIC MONOLITHIC CAPACITORS EIA/E CA-469-D (Revision of EIA-469-C) APRIL 2006 Electronic Cornpanen it may include many finishing lots, depending on the control document. Interban
2、d dimension: The distance between opposite end metallization bands on a capacitor element. Interface: The junction of two layers in a layered device, for example, the junction of electrode to dielectric layers or between two ceramic sheet layers. Intermetallic: A solution of two metallic elements fo
3、rmed during reflow or due to certain other conditions involving temperature and time, for example, the copper/tin intermetallic formed between a copper surface and a tin/lead solder when the solder is reflowed against the copper surface. Knitline: Generally, the bonding interface between two layers
4、of bondable materials; these may be the same, similar, or different materials. Specifically, in ceramic multilayer capacitors, the interface of bonding between two ceramic sheets or a ceramic and metallic interface. Knitline delamination: Specifically, a delamination that occurs in one of the knitli
5、nes of an end margin, in the same plane as an opposed electrode. Leaching: The erosion of end metal from a chip capacitor due to the action of molten solder, wherein the end metal is dissolved and put into solution with the solder. Length: The dimension running from termination to termination. In so
6、me chip capacitor designs, the length may be less than the width of the element. Lot: The general designation of a quantity of product which is of the same raw material origin, design and lot date code, and was manufactured as a uniquely designated group through the same processes. This could be a c
7、hip lot, a finishing lot, or an inspection lot. Lot date code: A designation used for lot identification that is made up of following sequence: 1) a 2-digit year code; 2) a 2-digit week code; 3) an alpha or alphanumeric code that is unique for one lot manufactured during a given year and week, e.g.,
8、 9305ZX, 931 5A7, 91 51 L, etc. This identifier must be printed on each part or each package, and on all pertinent data, photographs, samples, etc. Margin: The ceramic portion of a chip element which envelopes the active area. Metallization band: The portion of the end metallization which extends al
9、ong the exterior of the chip from the end of the chip element toward its longitudinal center for distances varying generally from 0.25 mm to 1 .O2 mm (0.01 in to 0.04 in). Microcrack: A very fine narrow crack in the ceramic that is visible only at relatively high magnifications (generally above 150X
10、) with the aid of indirect or dark field or polarized lighting. True Microcrack occur due to internal chip element stresses or relief of such stresses. Mounting: The process, during DPA, consisting of setting the sample specimens up on an adhesive surface and surrounding them with a retainer ring, r
11、eady for pouring of the potting medium. Opposed electrodes: See 3.28, Electrically opposed electrodes. Overlap view: The longitudinal sectional view of monolithic capacitors, hybrids or leaded, showing the overlapped electrode edges, end margins, end metallizations, and chip to lead solder joint, th
12、e plane being perpendicular to the electrodes and ceramic layers (see figure C.1.). -,-,- EIA-469-D Page 7 Pinhole: By definition, an open cavity in the ceramic cover plate, generally circular in shape, which is no larger than 0.05 mm (0.002 in) in diameter and has appreciable depth. Potting: See 3.
13、1 O, Casting. Potting medium: See 3.1 1, Casting material. Pull-out: The undesirable shattering, crumbling, and removal of materials from the specimen surface during abrasive sectioning or polishing. this is a problem particularly around voids, delaminations or other unsupported edges. Random sample
14、: A group of specimens drawn from a population of similar specimens (a lot) without regard for any selection principle or plan, where each individual has an equal chance of being chosen or passed over. Sample: A group of specimens drawn from a much larger group of similar specimens for the purpose o
15、f gathering information pertinent to the large group (population). Sample specimen: See 3.63, Sample unit. Sample unit: One member of a sample such as a capacitor. A sample of 20 pieces has 20 sample units. Scavenging: The action of molten solder upon chip capacitor end metal, by which the solder di
16、ssolves and takes all or part of the end metal into solution. Side margin: The portion of the ceramic envelope which is parallel to the thickness by length plane and which extends from the side of the electrodes to the outside edge of the chip element. Also see 3.50, Margin. Side margin view: The tr
17、ansverse sectional view of a sectioned sample unit, showing the side margins, cover plates and electrode edges. This is perpendicular to the overlap view and the electrode plane (see figure C.2.). Solder fill: The bulk of solder metal which occupies the space between a capacitor lead wire and the ca
18、pacitor element, which constitutes the solder joint between lead and capacitor element. Solder fillet: The externally visible portion of the solder metal which attaches the lead wire to the capacitor element and is characterized by a smooth and tapering convergence of solder metal with lead wire and
19、 capacitor element, the surface of the solder often being somewhat concave. Solder wetting: The condition whereby molten solder metal and a heated base metal surface fuse, forming an atomic interface (usually in the presence of a flux such as rosin). The liquid solder forms a dihedral angle with the
20、 base metal surface, generally less than 75“, for adequate solder-to-base metal bonding and with the anchorage area between base metal and solder ideally being 100%. Stress relief cracking: Cracks generally seen in the overlap view, but also in the side margin view, associated usually with the cover
21、 plates and the outer two or three electrodes. These are artifacts of the sectioning process due to grinding samples without decapsulation before mounting or due to inadequate edge support. They are not defects and must not be assessed as such. Striations: Longitudinal grooves in the side margin cer
22、amic surface at the layer interfaces, where layer-to- layer adhesion was disturbed during laminator chip ejection, chip dicing from a multichip pad, or chip handling before chip firing. These are distinguishable from delaminations in that the bottom of striations are visibly firing bonded, while the
23、 bottoms of delaminations or cracks cannot be visually determined. Subsample: A part of a total sample distinguishable from the remainder of the sample by a consideration such as the orientation of the view or plane of inspection, or by some separate requirement such as solderability testing which d
24、oes not pertain to the other DPA sample units. -,-,- EIA-469-D Page 8 Surface fracturing: Shallow, oblique cracking of ceramic between electrodes and in cover plates due to grinding stresses or chatter of the potted sample on the moving surface of the abrasive grit where the sample may alternately g
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