IC资料-S5L841F CHIP Audio - SAMSUNG.pdf
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1、S5L841F DIGITAL AUDIO DECODER FOR FLASH MEMORY MEDIA USERS MANUAL Revision 0 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omission
2、s, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to
3、 reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor
4、 does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. “Typical“ parameters can and do vary in different applications. All operating par
5、ameters, including “Typicals“ must be validated for each customer application by the customers technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sus
6、tain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung an
7、d its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized u
8、se, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. S5L841F 16-Bit CMOS Microcontroller Users Manual, Revision 0 Publication Number: 20-S5-L841F-032004 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduc
9、ed, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics microcontroller business has been awarded full ISO-14001 certification (BVQ1 C
10、ertificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Lee, Giheung-Eup Yongin-City Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(331)-209-1934 FAX: (8
11、2)-(331)-209-1899 Home-Page URL: Http:/ Printed in the Republic of Korea S5L841F iii Preface The S5L841F Users Manual is designed for application designers and programmers who are using the S5L841F for application development. It is organized in two main parts: Part I Programming Model Part II Hardw
12、are Descriptions Part I contains software-related information to familiarize you with the microcontrollers architecture, programming model, instruction set, and interrupt structure. It has nine chapters: Chapter 1 Product Overview Chapter 2 CalmRISC16 Programmers Model Chapter 3 CalmRISC16 Instructi
13、on Set Chapter 4 MAC2424 Instruction Set Chapter 5 CalmADM3 Chapter 1, “Product Overview,“ is a high-level introduction to S5L841F with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, “ CalmRISC16 Programmers Model,
14、“ describes the main features of CalmRISC16. Chapter 3, “ CalmRISC16 Instruction Set,“ describes the features and conventions of the instruction set used for CalmRISC16 processor. Chapter 4, “ MAC2424 Instruction Set,“ describes the features and conventions of the instruction set used for MAC2424 DS
15、P coprocessor. Chapter 5, “ CalmADM3,“ describes the features of Audio DSP Module. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the CalmRISC16-series processor family and are reading this
16、manual for the first time, we recommend that you first read Chapters 1, 2 and 5 carefully. Then, briefly look over the detailed information in Chapters 3, and 4. Later, you can reference the information in Part I as necessary. Part II “hardware Descriptions,“ has detailed information about specific
17、hardware components of the S5L841F. Also included in Part II are electrical, mechanical. It has 21 chapters: Chapter 6 Clock the instruction that immediately follows BNZD will be executed always regardless of whether BNZD is taken or not. 15 14 13 12 11109 8 7 6 0 1 1 0 0 0 1 1 H 0 Operation: if(H =
18、 R6) if(Z0 != 0) PC := PC + 2 + R6 := R6 1 Z0 := (R6-1) = 0) else / H = R7 Same mechanism as the case R6 H is a register specifier denoting either R6 or R7. Exceptions: None Notes: When BNZD checks if H is zero by looking up the Z0 (for R6) or Z1 (for R7) bit in SR, these flags are updated as BNZD d
19、ecrements the value of the register. For the first iteration, however, the user is responsible for resetting the flag, Z0 or Z1, before the loop starts execution. CalmRISC16 INSTRUCTION SET S5L841F (Preliminary Spec) 3-34 BR Conditional Branch Format: BRtype Description: The BR (Conditional Branch)
20、instruction is used to change the program flow conditionally or unconditionally. The allowed forms of the instruction include BRA (always), BRAD (always with delay slot), BRT (when T bit is set), BRTD (when T bit is set, with delay slot), BRF (when T bit is clear), and BRFD (when T bit is clear, wit
21、h delay slot). The branch target address is calculated by 1. sign-extending to 22 bits 2. adding this to the PC (which contains the address of the branch instruction plus 1) 15 14 13 12 11 109 0 1 1 0 D Operation: if (Condition) PC := PC + 2 + Here, the field determines whether this branch is BRA (0
22、1), BRF (10), or BRT (11). If D is set, the branch instruction has one branch delay slot, meaning that the instruction following the branch will be executed always, regardless of the branch outcome. If D is clear, the immediately following instruction is NOT executed if the branch is taken. Exceptio
23、ns: None Notes: None S5L841F (Preliminary Spec) CalmRISC16 INSTRUCTION SET 3-35 BRA EC Branch on External Condition Format: BRA(D) EC:2 Description: The BRA EC (Branch on External Condition) instruction is used to change the program flow when a certain external condition is set. A typical usage of t
24、his instruction is to branch after a coprocessor operation as shown below: COP NOP NOP BRA EC0 OVERFLOW . OVERFLOW: . . The BRA EC instruction checks the specified external condition (instead of checking the T bit as other branch instructions) and branch to the specified program address. There can b
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