IC资料-XC61C Series LOW VOLTAGE DETECTORS.pdf
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1、 71 GENERAL DESCRIPTION The XC61C series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N-channel open drain output configurations are available.
2、APPLICATIONS Microprocessor reset circuitry Memory battery back-up circuits Power-on reset circuits Power failure detection System battery life and charge voltage monitors TYPICAL PERFORMANCE CHARACTERISTICS FEATURES Highly Accurate : 2% Low Power Consumption : 0.7A (TYP.) VIN=1.5V Detect Voltage Ra
3、nge : 0.8V 1.5V in 100mV increments(Low Voltage) : 1.6V6.0V in 100mV increments(Standard Voltage) Operating Voltage Range : 0.7V 6.0V(Low Voltage) : 0.7V10.0V(Standard Voltage) Detect Voltage Temperature Characteristics : 100ppm/ (TYP.) Output Configuration : N-channel open drain or CMOS Ultra Small
4、 Packages : SSOT-24 (150mW) super mini-mold : SOT-23 (150mW) mini-mold : SOT-89 (500mW) mini-power mold : TO-92 ( 300mW ) : USP-6B (100mW) CMOS Highly Accurate :2% Low Power Consumption :0.7A (VIN=1.5V) TYPICAL APPLICATION CIRCUITS 72 XC61C Series PIN NUMBER SSOT-24 SOT-23 SOT-89 TO-92(T) TO-92(L) U
5、SP-6B PIN NAME FUNCTION 2 3 2 2 1 5 VIN Supply Voltage 4 2 3 3 2 1 VSS Ground 1 1 1 1 3 3 VOUT Output 3 - - - - 2,4,6NC No Connection DESIGNATOR DESCRIPTION SYMBOL DESCRIPTION C : CMOS output Output Configuration N : N-ch open drain output : e.g.0.9V 0, 9 Detect Voltage 08 60 : e.g.1.5V 1, 5 Output
6、Delay 0 : No delay Detect Accuracy 2 : Within 2% N : SSOT-24 (SC-82) M : SOT-23 P : SOT-89 T : TO-92 (Standard) L : TO-92 (Custom pin configuration) Package D : USP-6B R : Embossed tape , Standard feed L : Embossed tape , Reverse feed H : Paper type (TO-92) Device Orientation B : Bag (TO-92) PIN CON
7、FIGURATION PIN ASSIGNMENT PRODUCT CLASSIFICATION Ordering Information XC61 *Please use the circuit without connecting the heat dissipation pad. If the pad needs to be connected to other pins, it should be noted that the pin configuration of the USP-6B package is different depending on the IC series.
8、 Please refer to Contents-2. NC6 VIN5 NC4 1VSS 2NC 3VOUT 73 XC61C Series PACKAGING INFORMATION SSOT-24 (SC-82) SOT-23 74 XC61C Series SOT-89 TO-92 PACKAGING INFORMATION (Continued) 75 XC61C Series USP-6B PACKAGING INFORMATION (Continued) 76 XC61C Series CMOS Output (XC61CC series) N-Channel Open Dra
9、in Output (XC61CN series) MARK CONFIGURATION VOLTAGE(V) MARK CONFIGURATION VOLTAGE(V) A CMOS 0.X K N-ch 0.X B CMOS 1.X L N-ch 1.X MARK VOLTAGE(V)MARK VOLTAGE(V) 0 X.0 5 X.5 1 X.1 6 X.6 2 X.2 7 X.7 3 X.3 8 X.8 4 X.4 9 X.9 MARK 3 MARK VOLTAGE (V) 0 9 0.9 1 5 1.5 MARK OUTPUT CONFIGURATION C CMOS N N-ch
10、 DESIGNATOR DELAY TIME 0 No delay MARK DETECT VOLTAGE ACCURACY 2 Within 2% MARK PRODUCTION YEAR 3 2003 4 2004 Represents a least significant digit of production year Represents integer of output voltage and detect voltage Represents decimal number of detect voltage Based on internal standards ( SSOT
11、-24 excepted ) Represents production lot number 0 to 9, A to Z repeated (G,I,J,O,Q,W excepted) TO-92 Represents production lot number 0 to 9, A to Z repeated (G,I,J,O,Q,W excepted) Represents output configuration Represents detect voltage Represents delay time Represents detect voltage accuracy MAKI
12、NG RULE SSOT-24, SOT-23, SOT-89 12 34 12 3 123 77 XC61C Series MARK PRODUCT SERIES 1 C XC61Cxxx0xDx MARK OUTPUT CONFIGURATIONPRODUCT SERIES C CMOS XC61CCxx0xDx N N-ch XC61CNxx0xDx MARK Voltage (V) PRODUCT SERIES 3 3 3.3 XC61Cx330xDx 5 0 5.0 XC61Cx500xDx USP-6B , Represents product series Represents
13、output configuration ,Represents detect voltage (example) Represents production lot number 0 to 9, A to Z repeated (G,I,J,O,Q,W excepted) Note: No character inversion used. MARKING RULE (Continued) USP-6B (TOP VIEW) 78 XC61C Series *1: Low voltage *2: Standard voltage PARAMETER SYMBOL RATINGS UNITS
14、*1 9.0 Input Voltage *2 VIN 12.0 V *1 50 Output Current *2 IOUT 50 mA CMOS VSS -0.3 VIN +0.3 N-ch Open Drain Output *1 VSS -0.3 9.0 Output Voltage N-ch Open Drain Output *2 VOUT VSS -0.3 12.0 V SSOT-24 150 SOT-23 150 SOT-89 500 TO-92 300 Power Dissipation USP-6B Pd 100 mW Operating Temperature Range
15、 Topr -40+85 Strage Temperature Range Tstg -40+125 BLOCK DIAGRAMS ABSOLUTE MAXIMUM RATINGS Ta = 25 (1)CMOS Output (2)N-ch Open Drain Output 79 XC61C Series PARAMETER SYMBOL CONDITIONS MIN.TYP. MAX. UNITSCIRCUITS Detect Voltage VDF VDF x 0.98 VDF VDF x 1.02 V 1 Hysteresis Range VHYS VDF x 0.02 VDF x
16、0.05 VDF x 0.08 V 1 VIN = 1.5V - 0.7 2.3 = 2.0V - 0.8 2.7 = 3.0V - 0.9 3.0 = 4.0V - 1.0 3.2 Supply Current ISS = 5.0V - 1.1 3.6 A2 Low Voltage : VDF(T) = 0.8V to 1.5V 0.7 - 6.0 Operating Voltage VIN Standard Voltage : VDF(T) = 1.6V to 6.0V0.7 - 10.0 V 1 VIN = 0.7V0.100.80 - N-ch VDS = 0.5V VIN = 1.0
17、V0.852.70 - 3 Output Current (Low Voltage) CMOS, P-ch VDS = 2.1V VIN = 6.0V- -7.5 -1.5 4 VIN = 1.0V1.0 2.2 - VIN = 2.0V3.0 7.7 - VIN = 3.0V5.0 10.1 - VIN = 4.0V6.0 11.5 - N-ch VDS = 0.5V VIN = 5.0V7.0 13.0 - 3 Output Current (Standard Voltage) IOUT CMOS, P-ch VDS = 2.1V VIN = 8.0V- -10.0 -2.0 mA 4 T
18、emperature Characteristics VDF ToprVDF -40 Topr 85 - 100 - ppm/ - Delay Time (VDR VOUT inversion) tDLY - - 0.2 ms 5 ELECTRICAL CHARACTERISTICS VDF (T) = 0.9 to 1.5V 2% NOTE : VDF (T) : Setting detect voltage Release Voltage : VDR = VDF + VHYS Ta=25 80 XC61C Series OPERATIONAL EXPLANATION CMOS output
19、 When input voltage (VIN) rises above detect voltage (VDF), output voltage (VOUT) will be equal to VIN. ( A condition of high impedance exists with N-ch open drain output configurations. ) When input voltage (VIN) falls below detect voltage (VDF), output voltage (VOUT) will be equal to the ground vo
20、ltage (VSS) level. When input voltage (VIN) falls to a level below that of the minimum operating voltage (VMIN), output will become unstable. In this condition, VIN will equal the pulled-up output ( should output be pulled-up.) When input voltage (VIN) rises above the ground voltage (VSS) level, out
21、put will be unstable at levels below the minimum operating voltage (VMIN). Between the VMIN and detect release voltage (VDR) levels, the ground voltage (VSS) level will be maintained. When input voltage (VIN) rises above detect release voltage (VDR), output voltage (VOUT) will be equal to VIN. ( A c
22、ondition of high impedance exists with N-ch open drain output configurations. ) The difference between VDR and VDF represents the hysteresis range. Timing Chart 81 XC61C Series NOTES ON USE 1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or
23、permanent damage to the device. 2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. ( refer to the Oscillation Description (1) below ) 3. When a resistor is connect
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