IEEE-1076.3-1997.pdf
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1、 The Institute of Electrical and Electronics Engineers, Inc. 345 East 47th Street, New York, NY 10017-2394, USA Copyright 1997 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 1997. Printed in the United States of America. ISBN 1-55937-923-5 No part of th
2、is publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. IEEE Std 1076.3-1997 IEEE Standard VHDL Synthesis Packages Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 20 March
3、 1997 IEEE Standards Board Abstract: The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VH
4、DL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164- 1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arith-
5、metic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications. Keywords: interpretations, metalogical values, numeric VHDL vector types, signed, synthesi
6、s, un- signed Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/25/2007 02:58:31 MDTNo reproduction or networking permitted without license from IHS -,-,- IEEE Standards docum
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19、gineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/25/2007 02:58:31 MDTNo reproduction or networking permitted without license from IHS -,-,- iii Introduction (This introduction is not a part of IEEE Std 1076.3-1997, IEEE Standard V
20、HDL Synthesis Packages.) This standard, IEEE Std 1076.3-1997, supports the synthesis and verication of hardware designs, by den- ing vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. The standardization activity
21、started during the development of IEEE Std 1076-1993, IEEE Standard VHDL Language Reference Manual, to address a number of issues in the synthesis area that could not be ade- quately addressed within the scope of the main 1076 project. The initial Synthesis Special Interest Group (SSIG) analyzed a w
22、ide range of requirements and grouped them in four categories: a)Standard Interpretations of IEEE Std 1164-1993 values for synthesis b)Numeric types for synthesis c)Special attribute semantics d)Constraint specication Consensus was reached only on solutions presented for categories a) and b). The la
23、rge working group then commissioned a Pilot Team to drive the standardization effort. The three standardization chapters (North America, Europe, and Asia-Pacic) were all represented in the Pilot Team. The active members of the Pilot Team were the following: Alex N. Zamrescu, Chair The hard work and
24、professionalism of the Pilot Team members contributed signicantly to the nal result. Although the Working Group met regularly and voted on all major issues, the Pilot Team also extensively used electronic mail, a common repository, and several World Wide Web pages to accelerate the completely volunt
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