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1、 SURFACE VEHICLE RECOMMENDED PRACTICE Physical Layer, 250K bits/s, Twisted Shielded Pair SAE Technical Standards Board Rules provide that: “This report is published by SAE to advance the state of technical and engineering sciences. The use of this report is entirely voluntary, and its applicability
2、and suitability for any particular use, including any patent infringement arising therefrom, is the sole responsibility of the user.” SAE reviews each technical report at least every five years at which time it may be reaffirmed, revised, or cancelled. SAE invites your written comments and suggestio
3、ns. Copyright 2006 SAE International All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of SAE. TO PLACE A DO
4、CUMENT ORDER: Tel: 877-606-7323 (inside USA and Canada) Tel: 724-776-4970 (outside USA) Fax: 724-776-0790 Email: CustomerServicesae.org SAE WEB ADDRESS: http:/www.sae.org Issued 1994-12 Revised 2006-09 Superseding J1939-11 OCT1999 J1939-11 REV. SEP2006 Foreword This series of SAE Recommended Practic
5、es have been developed by the Truck and Bus Control and Communications Network Subcommittee of the Truck and Bus Electrical Committee. The objectives of the subcommittee are to develop information reports, recommended practices, and standards concerned with the requirements design and usage of devic
6、es which transmit electronic signals and control information among vehicle components. The usage of these recommended practices is not limited to truck and bus applications. Other applications may be accommodated with immediate support being provided for construction and agricultural equipment, and
7、stationary power systems. These SAE Recommended Practices are intended as a guide toward standard practice and are subject to change to keep pace with experience and technical advances. TABLE OF CONTENTS 1. Scope.3 1.1 Rationale3 2. Refererences 2.1 Applicable Publications3 2.1.1 SAE Publications3 2
8、.1.2 ISO Publication 3 2.1.3 Military Publication.4 2.2 Related Publication4 2.2.1 ISO Publication 4 3. Network Physical Description 4 3.1 Physical Layer4 3.2 Physical Media.4 3.3 Differential Voltage.4 3.4 Bus Levels4 3.5 Bus Levels During Arbitration 5 3.6 Common Mode Bus Voltage Range 5 3.7 Bus T
9、ermination.5 3.8 Internal Resistance 5 SAE J1939-11 Revised SEP2006 - 2 - 3.9 Differential Internal Resistance5 3.10 Internal Capacitance5 3.11 Differential Internal Capacitance6 3.12 Bit Time6 3.13 Internal Delay Time9 3.14 CAN Bit Timing Requirements.12 4. Functional Description12 5. Electrical Sp
10、ecification.13 5.1 Electrical Data13 5.1.1 Electronic Control Unit .13 5.1.1.1 Absolute Maximum Ratings .13 5.1.1.2 DC Parameters 13 5.1.1.3 AC Parameters.15 5.1.2 Bus VoltagesOperational15 5.1.3 Electrostatic Discharge (ESD) .15 5.1.4 Example Physical Layer Circuits15 5.2 Physical Media Parameters
11、.15 5.2.1 Bus Line .15 5.2.2 Topology.16 5.2.3 Terminating Resistor18 5.2.4 Shield Termination.18 5.2.5 ECU Type I and Type II Markings19 5.3 Connector Specifications .19 5.3.1 Connector Electrical Performance Requirements19 5.3.2 Connector Mechanical Requirements20 6. Conformance Tests21 6.1 Recess
12、ive Output of the ECUs22 6.2 Internal Resistance of CAN_H and CAN_L.22 6.3 Internal Differential Resistance23 6.4 Recessive Input Threshold of an ECU.23 6.5 Dominant Output of an ECU 24 6.6 Dominant Input Threshold of an ECU24 6.7 Internal Delay Time25 7. Discussion of Bus Faults25 7.1 Loss of Conne
13、ction to Network25 7.2 Node Power or Ground Loss .26 7.3 Unconnected Shield.26 7.4 Open and Short Failures26 8. Notes28 8.1 Marginal Indicia28 Appendix A Example Physical Layer Circuits29 A.1 Example 1 Physical Layer29 A.2 Example 2 Physical Layer30 A.3 Example 3 Physical Layer31 SAE J1939-11 Revise
14、d SEP2006 - 3 - Appendix B Recommended Cable Termination Procedure 32 Appendix C Recommended Cable Splice Procedure33 Appendix D Recommended Cable Repair Procedure.34 1. Scope These SAE Recommended Practices are intended for light- and heavy-duty vehicles on- or off-road as well as appropriate stati
15、onary applications which use vehicle derived components (e.g., generator sets). Vehicles of interest include but are not limited to: on- and off-highway trucks and their trailers; construction equipment; and agricultural equipment and implements. The purpose of these documents is to provide an open
16、interconnect system for electronic systems. It is the intention of these documents to allow electronic devices to communicate with each other by providing a standard architecture. 1.1 Rationale The J1939-11 document was reviewed during the five year SAE review period. The document was revised to add
17、 the Type I and Type II ECU information. The formatting was updated to the latest word processor program. 2. References General information regarding this series of recommended practices is found in SAE J1939. 2.1 Applicable Publications The following publications form a part of this specification t
18、o the extent specified herein. Unless otherwise indicated, the latest issue of SAE publications shall apply. 2.1.1 SAE PUBLICATIONS Available from SAE, 400 Commonwealth Drive, Warrendale, PA 15096-0001, Tel: 877-606-7323 (inside USA and Canada) or 724-776-4970 (outside USA), www.sae.org. SAE J1113-1
19、3Electromagnetic Compatibility Measurement Procedure for Vehicle Components Part 13Immunity to Electrostatic Discharge SAE J1128Low-Tension Primary Cable SAE J1939Recommended Practice for a Serial Control and Communication Vehicle Network 2.1.2 ISO PUBLICATION Available from ANSI, 25 West 43rd Stree
20、t, New York, NY 10036-8002, Tel: 212-642-4900, www.ansi.org. ISO 6722Road vehiclesUnscreened low-tension cables SAE J1939-11 Revised SEP2006 - 4 - 2.1.3 MILITARY PUBLICATION Available from DODSSP, Subscription Services Desk, Building 4D, 700 Robbins Avenue, Philadelphia, PA 19111-5094, Tel: 215-697-
21、2179, http:/assist.daps.mil or http:/stinet.dtic.mil. MIL-C-85485Cable, Electric, Filter Line 2.2 Related Publication The following publication is provided for information purposes only and is not a required part of this document. 2.2.1 ISO PUBLICATION Available from ANSI, 25 West 43rd Street, New Y
22、ork, NY 10036-8002, Tel: 212-642-4900, www.ansi.org. ISO 11898Road vehiclesInterchange of digital informationController area network (CAN) for high speed communication 3. Network Physical Description 3.1 Physical Layer The physical layer is a realization of an electrical connection of a number of EC
23、Us (Electronic Control Units) to a network. The total number of ECUs will be limited by electrical loads on the bus line. This maximum number of ECUs is fixed to 30, on a given segment, due to the definition of the electrical parameters given in the present specification 3.2 Physical Media This docu
24、ment defines a physical median of shielded twisted pair. These 2 wires have a characteristic impedance of 120 and are symmetrically driven with respect to the electrical currents. The designations of the individual wires are CAN_H and CAN_L. The names of the corresponding pins of the ECUs are also d
25、enoted by CAN_H and CAN_L, respectively. The third connection for the termination of the shield is denoted by CAN_SHLD. 3.3 Differential Voltage The voltages of CAN_H and CAN_L relative to ground of each individual ECU are denoted by VCAN_H and VCAN_L. The differential voltage between VCAN_H and VCA
26、N_L is defined by Equation 1: L_CANH_CANdiff VVV= (Eq. 1) 3.4 Bus Levels The bus lines can have one of the two logical states, recessive or dominant (see Figure 1). In the recessive state, VCAN_H and VCAN_L are fixed to a mean voltage level. Vdiff is approximately zero on a terminated bus. The reces
27、sive state is transmitted during bus idle or a recessive bit. SAE J1939-11 Revised SEP2006 - 5 - The dominant state is represented by a differential voltage greater than a minimum threshold. The dominant state overwrites the recessive state and is transmitted during a dominant bit. 3.5 Bus Levels Du
28、ring Arbitration A dominant and recessive bit imposed on the bus lines during a given bit time by two different ECUs will result in a dominant bit. FIGURE 1PHYSICAL BIT REPRESENTATION 3.6 Common Mode Bus Voltage Range The common mode bus voltage is defined as the boundary voltage levels of CAN_H and
29、 CAN_L, measured with respect to the individual ground of each ECU, for which proper operation is guaranteed when all ECUs are connected to the bus line. 3.7 Bus Termination The bus line is electrically terminated at each end with a load resistor denoted by RL (see Figure 2). Type I ECUs shall not c
30、ontain the bus termination resistor RL. Type II ECUs shall contain the bus termination resistor and if used shall be located only at one or both ends of a network. Type II ECUs shall be clearly marked as specified in Section 5.2.5. (Also see 5.2.3 for resistor characteristics.) 3.8 Internal Resistan
31、ce The internal resistance, Rin, of an ECU is defined as the resistance seen between CAN_H (or CAN_L) and ground during the recessive state, with the ECU disconnected from the bus line (see Figure 3). 3.9 Differential Internal Resistance The differential internal resistance, Rdiff, is defined as the
32、 resistance seen between CAN_H and CAN_L during the recessive state, with the ECU disconnected from the bus line (see Figure 4). 3.10 Internal Capacitance The internal capacitance, Cin, of an ECU is defined as the capacitance seen between CAN_H (or CAN_L) and ground during the recessive state, with
33、the ECU disconnected from the bus line (see Figure 3). SAE J1939-11 Revised SEP2006 - 6 - 3.11 Differential Internal Capacitance The differential internal capacitance, Cdiff, of an ECU is defined as the capacitance seen between CAN_H and CAN_L during the recessive state, with the ECU disconnected fr
34、om the bus line (see Figure 4). 3.12 Bit Time The bit time, tB, is defined as the duration of one bit (see Figure 5). Bus management functions executed within this bit time, such as ECU synchronization behavior, network transmission delay compensation, and sample point positioning, are defined by th
35、e programmable bit timing logic of the CAN protocol IC (Integrated Circuit). The bit time for this document is 4 s corresponding to 250 Kbit/s. Various names for the bit segments are used by suppliers of CAN protocol ICs and it is possible that two bit segments are defined as one. SAE J1939-11 Revis
36、ed SEP2006 - 7 - FIGURE 2PHYSICAL LAYER FUNCTIONAL SAE J1939-11 Revised SEP2006 - 8 - FIGURE 3ILLUSTRATION OF INTERNAL CAPACITANCE AND RESISTANCE OF AN ECU IN THE RECESSIVE STATE FIGURE 4ILLUSTRATION OF DIFFERENTIAL INTERNAL CAPACITANCE AND RESISTANCE OF AN ECU IN THE RECESSIVE STATE FIGURE 5PARTITI
37、ON OF THE BIT a. SYNC SEGThis part of the bit time is used to synchronize the various ECUs on the bus. An edge is expected within this bit segment. b. PROP SEGThis part of the bit time is used to compensate for the physical delay times within the network. These delay times are caused by the propagat
38、ion time of the bus line and the internal delay time of the ECUs. c. PHASE SEG1, PHASE SEG2These Phase-Buffer-Segments are used to compensate for phase-errors and can be lengthened or shortened by resynchronization. SAE J1939-11 Revised SEP2006 - 9 - d. Sample-PointThe Sample-Point is the point of t
39、ime at which the bus level is read and interpreted as the value of that respective bit. Its location is at the end of PHASE_SEG1. 3.13 Internal Delay Time The internal delay time of an ECU, tECU, is defined as the sum of all asynchronous delays that occur along the transmission and reception path of
40、 the individual ECUs, relative to the bit timing logic unit of the protocol IC. For more details, see Figure 6. a. SynchronizationHard Synchronization and Resynchronization are the two forms of synchronization. They obey the following rules: 1. Only one Synchronization within one bit time is allowed
41、. 2. An edge will be used for Synchronization only if the value detected at the previous Sample Point (previously read bus value) differs from the bus value immediately after the edge. 3. Hard Synchronization is performed during said edge whenever there is a recessive to dominant edge. 4. All other
42、recessive to dominant edges fulfilling rules 1 and 2 will be used for Resynchronization with the exception that a transmitter will not perform Resynchronization as a result of a recessive to dominant edge with a positive Phase Error if only recessive to dominant edges are used for Resynchronization.
43、 b. Synchronization Jump Width (SJW)As a result of Synchronization PHASE_SEG1 may be lengthened or PHASE_SEG2 may be shortened. The amount of lengthening or shortening of the Phase Buffer bit Segments has an upper bound given by the Synchronization Jump Width. The Synchronization Jump Width is less
44、than or equal to PHASE_SEG1. SAE J1939-11 Revised SEP2006 - 10 - FIGURE 6TIME RELATIONSHIP BETWEEN BIT TIMING LOGIC OF ECU A AND B DURING ARBITRATION SAE J1939-11 Revised SEP2006 - 11 - 3.14 CAN Bit Timing Requirements It is necessary to ensure that a reliable network can be constructed with compone
45、nts from multiple suppliers. Without any bit timing restrictions, different devices may not be able to properly receive and interpret valid messages. Under certain network conditions it may also be possible for a particular device to have unfair access to the network. In addition, it makes network m
46、anagement (system diagnostics) much more difficult. CAN chip suppliers also recommend that all devices on a given network be programmed with the same bit timing values. All CAN ICs divide the bit time into smaller sections defined as tq (time quantum). For most CAN ICs 1 tq = 250 ns (with a 16 MHz c
47、lock) (determined by oscillator frequency and baud rate prescaler). Therefore specific values for the bit timing registers need to be defined to ensure that a reliable network exists for all nodes based on the best tradeoffs between propagation delay and clock tolerance. Note that there are some dif
48、ferences in bit segment definition between manufacturers of CAN devices. It is recommended that a tq be selected which permits the sample point (see Figure 5) to be located as close to but not later than 7/8 of a bit time (0.875x4uS = 3.5uS). This provides the best tradeoff between propagation delay
49、 and clock tolerance. The following values are recommended for typical controller ICs running at standard clock frequencies. At other frequencies, different values may have to be selected to maintain the sample point as close as possible but not later than the preferred time. 16 MHz sample point = 0.875 tb tq=250 ns (16 tq/bit) tsync=250 ns (1 tq) TSEG1 = 3.25 s (13 tq) TSEG2 = 500 ns (2 tq) 20 MHz sample point = 0.85 tb tq = 200 ns (20 tq/bit) tsync = 200 ns (1 tq) TSEG1 = 3.2 s (16 tq) TSEG2 = 600 ns (3 tq) SJW = 1 tq (SJW
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