Signal Integrity Lab 2 (HFSS).ppt
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1、1,Signal Integrity Lab 2 Ansoft High Frequency Structure Simulator (HFSS),2,Driven Terminal Problem,Analyze two micro strip lines that pass through via. Analyze the impact of return loss and insertion loss. (S11, S21 ) Use the 4 layer PCB in the following stack up. Analyze the PCB at a size of 2 x 2
2、 inch,3,Stack up,1 mil = 0.001 inch, Signal trace width = 5 mil Signal to signal space = 20 mil,4,Configuration,Start HFSS Save file Insert HFSS design Setup solution type: Driven Terminal Setup grid to 0.1 inch,5,Structure Design,Draw a BOX at: 0, 0, 0, size: 2, 2, 0.005 inch. Assign material: FR4_
3、epoxy. Set transparent: 0.7 Rename it: FR4_1 Draw 2nd BOX at 0, 0, 0.005, size: 2, 2, 0.0014 inch. Assign material: Copper. Set transparent: 0.7 Rename it: GND1 Draw 3rd BOX at 0, 0, 0.0064, size: 2, 2, 0.047 inch. Assign material: FR4_epoxy. Set transparent: 0.7 Rename it: FR4_2 Select GND1 by clic
4、king in command history window. Click: Edit- copy, and Edit - Paste. Now, GND2 is copied from GND1 and is placed at the exact same location! Double Click GND2 (create box) at command history window. At property window, put 0, 0, 0.0534 as new origin. This moves GND2 to upper layer,6,Stack up Design,
5、Do the same thing to copy FR4_1 and make it FR4_3. Put new origin as: 0, 0, 0.0548 Now the stack up is ready. It has two ground layers and 3 FR4 layers. Grey color is for FR4 and Blue is for GND,Side view of PCB stackup,7,Add signal trace,Draw a BOX at: 0, 1, 0.0598, size: 1.005, 0.005, 0.0014 inch
6、Rename it: Trace1, Assign Material: Copper. Change the color to: RED Copy Trace1, and Paste it. Now you got trace2. Change trace2s original at 0.995, 1, 0 inch, size: 1.005, 0.005, -0.0014 inch Now Trace1 and Trace2 are on two different sides of the PCB. They are located at center and overlap each o
7、ther by 10mil. In order to see both traces, you need to set transparent property of all drawing to be 0.7,8,9,What is via and anti-via,What is via & anti-via What does via do? What does anti-via do?,10,Via: vertical connection between layers Barrel: conductive cylinder filling the drilled hole Pad:
8、connects the barrel to the component/plane/trace Antipad: clearance hole between via and no-connect metal layer,Barrel,Pad,Via pad does not contact plane; void is the anti-pad,Trace connected to pad on layer 1.,11,A Via might: Connect metal planes of the same potential (e.g., all ground planes condu
9、ctively attached) Carry a signal from a trace on one layer to another (e.g., every data signal must get from the silicon bump down to the motherboardand possibly through the motherboard!) Connect components (such as a capacitor) to a signal trace or a voltage plane.,12,Add via and anti-via,Click the
10、 cylinder icon, draw a cylinder between two traces. Change the current position to: 1, 1.0025, 0 inch, radius: 0.005 and height: 0.0598 inch. Assign the material: copper. Change the color: RED Rename it: via1 Do another cylinder (10mil radius), assign material: Fr4_epoxy, rename it: anti_via1 Two cy
11、linders overlap and center at same location. - this will cause a problem and confuse the software! Why?,13,Bolean function,The overlap of two different materials will cause design error. This can be corrected by using Boolean function subtract. In command history window, hold: Ctrl key and click: FR
12、4_1, FR4_2, FR4_3, GND1, GND2, anti_via1 This selects the 6 items above to perform a Boolean function Click: 3D Modeler - Boolean - Subtract,14,Bolean Function - subtract,Subtract window pops up. Move, FR4_1, FR4_2, FR4_3, GND1, GND2 to Blank Parts window Move anti_via1 to Tool Parts window Select “
13、Clone tool objects before subtracting” Why? Click “OK”,15,View - Visibility,After subtraction, graphic verification is hard since all the components overlap each other. (visibility setting can solve this problem) Click: View - visibility Visibility window pops up. Turn off the visibility on all FR4
14、and anti_via1 It is verified that via passed through two layers of ground without touching it,16,Question.,The overlap issue between FR4, GND and anti-via is solved. Theres another overlap error. Which one?,17,Overlap problem 2,Theres overlap between anti-via and via. Use Boolean subtraction functio
15、n, subtract via from the anti-via. Dont forgot to “clone” the via Use the visibility command to verify that anti_via1 has a hole in the center.,18,Bolean function - unite,Hold Ctrl key and click: FR4_1, FR4_2, FR4_3, anti_via1 Click: 3D modeler - Boolean - unite All of above items will be united int
16、o one item. Name: FR4_1. ( the new name is the first item you selected ) You can only unite the items that touch each other and have same material Your field solution is more accurate and process is faster after you unite the similar items If you want to un-do the “unite”, go to command history wind
17、ow and delete the “unite” under FR4_1 Do the same thing to unite: trace1, trace2, via,19,Create 2nd trace,In command history window, click and select: trace1 Click: edit - copy, then click: paste Now, you have trace3 created at the exact same location of trace1. (they overlap each other) Click and s
18、elect: trace3 Click: Edit arrange - move Use the mouse, drag trace 3 in the positive Y direction 20mils. (note: DY = 0.02 indicator at bottom right) To verify the move, in the command history window, double click the move command.,20,Create 2nd trace, cont.,Now, the sub window pops up. Make sure the
19、 move vector is 0, 0.02, 0 This makes the 2nd trace 20mil away from 1st trace. What is the air gap size between the traces?,21,2nd Anti-via,Create an anti-via for the 2nd trace. The center location should be 0, 1.023, 0 Review slide 10 for creating an anti-via Rename the new item: anti_via2 Theres a
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