Interrupt Generation Using the AT91 TC.pdf
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1、 2683BATARM03-10-03 Interrupt Generation Using the AT91 Timer/Counter Introduction This application note describes how to generate an Interrupt by using the Timer/Counter (TC) in the AT91 series of microcontrollers. Timer/Counter Overview The AT91 series features a Timer/Counter block, which include
2、s three identical 16-bit timer counter channels. Each channel can be independently programmed, through its two operating modes, to perform a wide range of functions including frequency mea- surement, event counting, interval measurement, pulse generation, delay timing, pulse width modulation and int
3、errupt generation. Each Timer Counter channel has 3 external clock inputs, 5 internal clock inputs, and 2 multi purpose input/output signals, which can be configured by the user. Each channel drives an internal interrupt signal, which can be programmed to generate processor interrupts via the Advanc
4、ed Interrupt Controller (AIC). The three Timer Counter chan- nels are independent and identical in operation. Each Timer Counter channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0
5、xFFFF and passes to 0x0000, an overflow occurs and the bit COVFS in TCx_SR (Status Register) is set. The current value of the counter is accessible in real-time by reading TCx_CV. A trig- ger can reset the counter. In this case, the counter value passes to 0x0000 on the next valid edge of the select
6、ed clock. AT91 ARM Thumb Microcontroller Application Note 2Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 Operating ModesEach Timer Counter channel can operate independently in two different modes: Capture Mode allows measurement on signals Waveform Mode allows wave generation The
7、Timer Counter Operating Mode is programmed with the WAVE bit in the TC Chan- nel Mode Register (TCx_CMR). In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. Trigg
8、erA trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. Common TriggersThe following triggers are common to both operating modes: Software Trigger: Each channel has a software trigger, ava
9、ilable by setting SWTRG in TCx_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is impl
10、emented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TCx_CMR. External TriggerThe Timer Counter channel can also be configured to have an external trigger. In Cap- ture Mode, the external trigger signal can be selected between TIOA and TIO
11、B. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trig- ger by setting ENETRG in TCx_CMR. If an external trigger is used, the duration of the pulses must be longer than the system c
12、lock (MCK) period in order to be detected. 3 Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 Timer/Counter Block Diagram Figure 1. Timer/Counter Block Diagram Timer/Counter Channel 0 Timer/Counter Channel 1 Timer/Counter Channel 2 SYNC Parallel I/O Controller TC1XC1S TC0XC0S TC2XC2S
13、 INT INT INT TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 XC0 XC1 XC2 XC0 XC1 XC2 XC0 XC1 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA1 TIOA2 TIOA0 TIOA2 TIOA0 TIOA1 Advanced Interrupt Controller TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 Timer Counter Block TIOA TIOB TIOA TIOB T
14、IOA TIOB SYNC SYNC MCK/8 MCK/32 MCK/128 MCK/1024 MCK/2 4Interrupt Generation Using AT91 Timer/Counter 2683BATARM03-10-03 Clock SourceEach channel can independently select an internal or external clock source for its counter: Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, MCK/1024 External cl
15、ock signals: XC0, XC1 or XC2 The three-bit TCCLKS field of the mode register TCx_CMR determines whether the counter is clocked by one of the five internal clock sources (MCK/x) or one of the three external clock sources (TCLKx). The selected clock can be inverted with the CLKI bit in TCx_CMR (Channe
16、l Mode Reg- ister). This enables counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). Note: In all cases, if an external clock is used, the
17、 duration of each of its levels must be longer than the system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than the system clock (MCK). Figure 2. Timer/Counter Clock Source The maximal counter duration when an internal clock is used, is determined by the inter-
18、nal clock MCK and the prescaler number: where FTC is in Hz. Table 1. Maximum Counter Duration for Various MCK MCK5 MHz10 MHz20 MHz33 MHz66 MHz MCK/2 26.21ms13.10ms6.55ms3.97ms1.98ms MCK/8104.8ms52.4ms26.22ms14.89ms7.45ms MCK/16419.4ms209.7ms104.86ms63.86ms31.98ms MCK/1281.68s838.8ms420.4ms254.2ms127
19、.1ms MCK/102413.42s6.71s3.36ms2.03s1.02s MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 XC0 XC1 XC2 CLKS 1 Clock Counter 000 001 010 011 100 101 110 111 00 01 10 13 0 1 TCx_MR2:0 Burst TCx_MR5:4 CLKI TCx_MR3 BURSTCLK maximal counter duration (seconds)216FTC= counter resolution1=FTC 5 Interrupt Generation Using
20、 AT91 Timer/Counter 2683BATARM03-10-03 Timer Interrupt Generation Each Timer/Counter channel drives an internal interrupt signal which can be pro- grammed to generate processor interrupts via the AIC (Advanced Interrupt Controller). Each Timer/Counter channel contains a total of 8 interrupts, which
21、can be enabled or disabled from the registers TCx_IER and TCx_IDR. The interrupts are available accord- ing to the operating mode as shown below in Table 2. Application ExampleUse the AT91 Timer/Counter to generate an interrupt and blink one LED every 1s. This application example is based on the AT9
22、1EB40A Evaluation Board but is applicable to all AT91 products. Timer configuration The RC can generate a trigger if bit CPCTRG in the TC Mode Register is set to 1. A trig- ger resets the counter so that RC can control the timer period needed. The RC compare interrupt will be used to generate an int
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