IT8888G_V0.9.pdf
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1、Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales representatives. IT8888G PCI-to-ISA Bridge Chip (Code Name: Golden Gate) Preliminary Specification V0.9 ITE TECH. INC. Copyright ? 2005 ITE Tech. Inc. This is Preliminary document relea
2、se. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to ITEs Standard Terms and Condi
3、tions, a copy of which is included in the back of this document. ITE, IT8888G is a trademark of ITE Tech. Inc. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtaine
4、d from: ITE Tech. Inc. Phone: (02) 2912-6889 Marketing Department Fax: (02) 2910-2551, 2910-2552 8F, No. 233-1, Bao Chiao RD., Hsin Tien, Taipei County 231, Taiwan, R.O.C. If you have any marketing or sales questions, please contact: P.Y. Chang , at ITE Taiwan: E-mail: .tw, Tel: 886-2-29126889 X6052
5、, Fax: 886-2-29102551 To find out more about ITE, visit our World Wide Web at: http:/.tw Or e-mail .tw for more product information/services .twIT8888G V0.91 Revision History Revision History Section Revision Page 1 ? Added a new feature, “SM Bus”. 1 3 ? Chapter 3, Pin Configuration, was revised. 5
6、? Table 4-3, Miscellaneous Signals, was revised. 10 ? Table 4-5, IT8888G Pins Listed in Numeric Order, was revised. 11 4 ? Table4-6, Power-On-Strap Settings, was revised. 12 .twIT8888G V0.9i Contents CONTENTS 1.Features .1 2.General Description.3 3.Pin Configuration .5 4.Pin Description.7 5.Function
7、al Description.13 5.1PCI Slave Interface.13 5.2PCI Master Interface.13 5.3PCI Parity14 5.4Positively Decode Spaces14 5.5Subtractive Decode.14 5.6PC/PCI DMA (PPDMA) Slave Controller14 5.7Distributed DMA (DDMA) Slave Controller.15 5.8Type-F DMA Timing15 5.9ISA Bus I/O Recovery Time15 5.10 ISA Bus Arbi
8、ter15 5.11 SMB Boot ROM Configuration16 5.12 Serialized IRQ.18 5.13 NOGO and CLKRUN#18 5.14 Optional FLASH ROM Interface19 5.15 Testability19 6.Register Description.21 6.1Configuration Register Map21 6.2Access Configuration Registers22 6.3Configuration Registers Description.24 6.3.1Device/Vendor ID
9、Register.24 6.3.2Status / Command Register.24 6.3.3Class Code/ Revision ID Register25 6.3.4Header Type/ Primary MLT/ Cache Line Size Register.26 6.3.5Subsystem Device/Vendor ID Register26 6.3.6DDMA Slave Channel_1 Register / DDMA Slave Channel_0 Register.26 6.3.7DDMA Slave Channel_3 Register / DDMA
10、Slave Channel_2 Register.27 6.3.8DDMA Slave Channel_5 Register / DMA Type-F Timing / PPD Register28 6.3.9DDMA Slave Channel_7 Register / DDMA Slave Channel_6 Register.29 6.3.10ROM / ISA Spaces and Timing Control29 6.3.11Retry/Discard Timers, Misc. Control Register31 6.3.12Positively Decoded IO_Space
11、_0 Register.33 6.3.13Positively Decoded IO_Space_1 Register.33 6.3.14Positively Decoded IO_Space_2 Register.34 6.3.15Positively Decoded IO_Space_3 Register.34 6.3.16Positively Decoded IO_Space_4 Register.35 6.3.17Positively Decoded IO_Space_5 Register.35 6.3.18Positively Decoded Memory_Space_0 Regis
12、ter35 6.3.19Positively Decoded Memory_Space_1 Register36 6.3.20Positively Decoded Memory_Space_2 Register36 6.3.21Positively Decoded Memory_Space_3 Register37 6.3.22Undefined Register.37 6.4DDMA Slave Registers Description38 7.Characteristics.41 7.1DC Electrical Characteristics42 7.2AC Characteristi
13、cs43 7.3Waveforms46 8.Package Information61 .twIT8888G V0.9 ii IT8888G 9.Ordering Information63 FIGURES Figure 2-1. IC Block Diagram4 Figure 6-1. PCI Configuration Register Structure.22 Figure 6-2. PCI Configuration Access Mechanism #123 Figure 7-1. PCI Bus Interface Timing46 Figure 7-2. PCI Configu
14、ration Write / Read Cycle46 Figure 7-3. DEVSEL# Decoding Speed47 Figure 7-4. PCI Memory Read from ISA Device when Delayed Transaction is disabled.47 Figure 7-5. PCI Memory Read from ISA Device when Delayed Transaction is enabled48 Figure 7-6. IT8888G Initiated Refresh Cycle.49 Figure 7-7 PCI I/O Rea
15、d from ISA device.49 Figure 7-8 PCI I/O Write to 8-bit ISA Device when Cfg_54=0b50 Figure 7-9. PCI I/O Write to 16-bit ISA Device when Cfg_54=1b.50 Figure 7-10. PCI Memory Read from 8-bit ISA Device.51 Figure 7-11. PCI Memory Read from 16-bit ISA Device.51 Figure 7-12. PCI Memory Write to 8-bit ISA
16、Device.52 Figure 7-13. PCI Memory Write to 16-bit ISA Device.52 Figure 7-14. DREQn/DACKn# Coding in PC/PCI DMA Function.53 Figure 7-15. DMA Read Operation in PC/PCI DMA (Memory Access to PCI with TC)53 Figure 7-16. ISA Master Memory Read from PCI in PC/PCI DMA (Retried and Normal Termination)54 Figu
17、re 7-17. DMA Read Operation in DDMA (Memory Access to PCI when DDMA-Concurrent is disabled.)55 Figure 7-18. DMA Read Operation in DDMA (Memory Access to PCI when both Delayed-Transaction and DDMA-Concurrent are enabled.)56 Figure 7-19. DMA Write Operation in DDMA (Memory Access to PCI when both Dela
18、yed-Transaction and DDMA-Concurrent are enabled.)57 Figure 7-20. ISA Master Write and Master-Initiated-Refresh Operation in DDMA (Memory Access to PCI when both Delayed-Transaction and DDMA-Concurrent are enabled.).58 Figure 7-21. Serialized IRQ Coding59 Figure 7-22 CLKRUN# Operation.59 Figure 7-23.
19、 SMB Serial E 2PROM Configuration Programming. 60 Figure 7-24 SMB Serial E 2PROM Interface Timing 60 TABLES Table 4-1. PCI Bus Interface Signals7 Table 4-2. ISA Bus Interface Signals9 Table 4-3. Miscellaneous Signals.10 Table 4-4. Power Signals11 Table 4-5. IT8888G Pins Listed in Numeric Order11 Tab
20、le 4-6. Power-On-Strap Settings.12 Table 6-1. IT8888G Configuration Register Map21 .twIT8888G V0.9 iii Contents Table 7-1. Recommended Operating Conditions42 Table 7-2. General DC Characteristics.42 Table 7-3. DC Electrical Characteristics.42 Table 7-4. AC Characteristics of PCI Interface Timing.43
21、Table 7-5. AC Characteristics of ISA Interface Timing (PIO Cycle)43 Table 7-6. AC Characteristics of ISA Interface Timing (DMA Cycle)44 Table 7-7. AC Characteristics of SMB Interface Timing.45 .tw IT8888G V0.9 ITPM-PN-200512 Specifications subject to Change without Notice By P.C. Lin, 4/28/2005 1 Fe
22、atures 1. Features PCI Interface - PCI Specification V. 2.1 compliant - Supports 32-bit PCI bus otherwise, tri-state. (input for IC test only) 5V M11 SMEMW# I/O, P/U 50K System Memory Write #. This signal is an output signal for access under 1MB; otherwise, tri-state. (input for IC test only) 5V M10
23、 BCLK O Bus Clock ISA bus clock equals to ? of PCI clock. 5V P13 BALE I/O, P/U 50K Buffer Address Latch Enable This signal is also used as power-on strapping select. 5V Table 4-3. Miscellaneous Signals Pin # Signal I/O Description Level A10 NOGO/ CLKRUN# I/O NOGO / Clock Run # The function selection
24、 of this pin is determined by Cfg_54h. When acting as NOGO, it is an input from chipset to disable the subtractive decode of the IT8888G; when acting as CLKRUN#, it is an input/output for the IT8888G to request PCICLK to keep running. 5V C9 SERIRQ I/O Serial IRQ This is Serialized IRQ for encoding p
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