IT8203R_V0.2.pdf
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1、Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales representatives. IT8203R Jumper Free Over Clock Controller Preliminary Specification 0.2 (For C Version Only) ITE TECH. INC. Copyright 2004 ITE, Inc. This is Preliminary document releas
2、e. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to ITEs Standard Terms and Condit
3、ions, a copy of which is included in the back of this document. ITE, IT8203R is a trademark of ITE Tech. Inc. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained
4、 from: ITE Tech. Inc. Phone: (02) 29126889 Marketing Department Fax:(02) 2910-2551, 2910-2552 8F, No. 233-1, Bao Chiao RD., Hsin Tien, Taipei County 231, Taiwan, R.O.C. If you have any marketing or sales questions, please contact: P.Y. Chang, at ITE Taiwan: E-mail: .tw, Tel: 886-2-29126889 X6052, Fa
5、x: 886-2-29102551 To find out more about ITE, visit our World Wide Web at: http:/.tw Or e-mail .tw for more product information/services .tw IT8203R V0.21 Revision History Revision History Section Revision Page No. - ?Add User-ID and Version ID registers (offset 0x28, 0x29 and 0x2a).- - ?In Dynamic
6、VID mode, VID Programmed Output Register (0x02) register supports minus VID output - .twIT8203R V0.2i Contents CONTENTS 1.Features 1 2.General Description3 3.Block Diagram5 4.Pin Configuration7 5.IT8203 Pin Descriptions.9 6.Register Description.11 6.1Register Description11 6.1.1VID Output Control Re
7、gister (VFOCR) Offset 0x00.12 6.1.2VID Programmed Output Register (VIDPOR) Offset 0x02.12 6.1.3VID Output Register (VIDOR) Offset 0x0312 6.1.4VID Input Register (VIDIR) Offset 0x0413 6.1.5GPIO A Control Register (GPIOACR) Offset 0x10.13 6.1.6GPIO B Control Register (GPIOBCR) Offset 0x11.13 6.1.7GPIO
8、 A Data Register (GPIOADR) Offset 0x12.14 6.1.8GPIO B Data Register (GPIOBDR) Offset 0x13.14 6.1.9GPIO A Output Type Register (GPIOAOTR) Offset 0x1415 6.1.10GPIO B Output Type Register (GPIOBOTR) Offset 0x1515 6.1.11GPIO A Pull-up Resister Control Register (GPIOAPUR) Offset 0x1616 6.1.12GPIO B Pull-
9、up Resister Control Register (GPIOBPUR) Offset 0x1716 6.1.13GPIO A Pull-down Resister Control Register (GPIOAPDR) Offset 0x18 .17 6.1.14GPIO B Pull-down Resister Control Register (GPIOBPDR) Offset 0x19 .17 6.1.15GPIO A and B Synchronize Control Register (GPIOSYNR) Offset 0x1A.18 6.1.16Watch-Dog Time
10、r Register (WDTR) Offset 0x2018 6.1.17Watch-Dog Timer Unit Register (WDTUR) Offset 0x2118 6.1.18Watch-Dog Timer Control Register (WDTCSR) Offset 0x2218 6.1.19User ID Register 1 (UIDR1) Offset 0x28.18 6.1.20User ID Register 2 (UIDR2) Offset 0x29.19 6.1.21Version ID Register (VERIDR) Offset 0x2a19 7.D
11、C Characteristics.21 8.AC Characteristics23 9.Package Information25 10. Ordering Information27 FIGURES Figure 8-1. SM Bus Waveform23 TABLES Table 4-1. Pins Listed in Numeric Order.8 Table 5-1. Pin Descriptions of VID Interface.9 Table 5-2. Pin Descriptions of General Purpose I/O.9 Table 5-3. Pin Des
12、criptions of SM Bus Interface.9 Table 5-4. Pin Description of Watch-Dog Reset9 Table 5-5. Pin Description of CPU Changing Detection9 .tw IT8203R V0.2 ii IT8203R Table 5-6. Pin Description of Power/Ground.9 Table 6-1. List of Over Clock Registers.11 Table 8-1. SM Bus AC Table.23 .tw IT8203R V0.2 ITPM
13、-PN-200329 Specifications subject to Change without Notice By Claire Yao, 10/27/2003 1 Features 1. Features Five VID input (VIDIN04) and five VID output (VIDOUT0VIDOUT4) pins Provides 10 GPIO pins Supports Auto-Recovery; build-in watch-dog timer and reset output signal pin Provides CPU changing dete
14、ct pin (SLOTOCC#) SM Bus interface 28-pin SSOP .tw IT8203R V0.2 2 .tw IT8203R V0.2 3 General Description 2. General Description For acquiring a better performance with a lower cost, “Over-Clocking“ gradually becomes a popular feature in the DIY market of PC motherboard. To do so, many interfaces on
15、motherboard such as PWM, CPU, chipset, clock generator, AGP, DIMM, etc should be well handled. Moreover, there is a trend to do “Jumperless“ Over-Clocking in the motherboard design. For matching the trend, ITE develops a series of Jumper Free Over Clock Controllers targeted on different environments
16、. Generally, these controllers cover the following features: - VID Interface and/or FID Interface handling - GPIO - Watch Dog Timers with Reset Signals for system auto-recovery from different situations - CPU changing detection .tw IT8203R V0.2 4 .tw IT8203R V0.2 5 Block Diagram 3. Block Diagram REG
17、ISTER CONTROLLER Watch-Dog Controller SCL SDA ASEL VIDIN40 VBAT GPIO09 VIDOUT40 RSTOUT# SLOTOCC# SM Bus Controller .tw IT8203R V0.2 6 .tw IT8203R V0.2 7 Pin Configuration 4. Pin Configuration 1 2 10 9 8 7 6 5 4 3 14 13 12 11 25 26 27 28 16 17 23 24 15 VBAT GPIO6 GPIO0 SCL SDA VIDIN3 VIDIN2 VIDIN1 VI
18、DIN0 GPIO3 GPIO4 VIDIN4 GPIO5 3VSBASEL VIDOUT0 GPIO1 GPIO2 GPIO9 GPIO8 GPIO7 VIDOUT3 VIDOUT2 VIDOUT1 RSTOUT# GND SLOTOCC# I T 8 2 0 3 R 20 21 22 18 19VIDOUT4 .tw IT8203R V0.2 8 IT8203R IT8203R Table 4-1. Pins Listed in Numeric Order Pin Signal Pin Signal Pin Signal Pin Signal 1 3VSB 8 VIDIN3 15 RSTO
19、UT# 22 VIDOUT1 2 GPIO3 9 VIDIN4 16 GND 23 VIDOUT0 3 GPIO4 10 GPIO0 17 SLOTOCC# 24 GPIO9 4 GPIO5 11 GPIO1 18 VBAT 25 GPIO8 5 VIDIN0 12 GPIO2 19 VIDOUT4 26 GPIO7 6 VIDIN1 13 SDA 20 VIDOUT3 27 GPIO6 7 VIDIN2 14 SCL 21 VIDOUT2 28 ASEL Table 4-2. Pins Listed in Alphabetical Order Pin Signal Pin Signal Pi
20、n Signal Pin Signal 1 3VSB 3 GPIO4 14 SCL 8 VIDIN3 28 ASEL 4 GPIO5 13 SDA 9 VIDIN4 16 GND 27 GPIO6 17 SLOTOCC# 23 VIDOUT0 10 GPIO0 26 GPIO7 18 VBAT 22 VIDOUT1 11 GPIO1 25 GPIO8 5 VIDIN0 21 VIDOUT2 12 GPIO2 24 GPIO9 6 VIDIN1 20 VIDOUT3 2 GPIO3 15 RSTOUT# 7 VIDIN2 19 VIDOUT4 .tw IT8203R V0.2 9 IT8203
21、Pin Descriptions 5. IT8203 Pin Descriptions Table 5-1. Pin Descriptions of VID Interface Pin(s) No. Symbol Attribute Description 5-9 VIDIN0 VIDIN4 I Voltage Identification Input Signals from CPU 19-23 VIDOUT4 VIDOUT0 OD12 Voltage Identification Output Signals to PWM Table 5-2. Pin Descriptions of Ge
22、neral Purpose I/O Pin(s) No. Symbol Attribute Description 10-12, 2-4, 27,26,25,24 GPIO0 GPIO9 IO12 General Purpose I/O pins GPIO5 is 3.3 V level Table 5-3. Pin Descriptions of SM Bus Interface Pin(s) No. Symbol Attribute Description 13 SDA IOD12 SM Bus Data Signal 14 SCL IK SM Bus Clock Signal 28 AS
23、EL OD12 Address Selector 0: 7 h37 1: 7 h4E Table 5-4. Pin Description of Watch-Dog Reset Pin(s) No. Symbol Attribute Description 15 RSTOUT# OD12 Watch-Dog Timeout Reset Output Signal Table 5-5. Pin Description of CPU Changing Detection Pin(s) No. Symbol Attribute Description 17 SLOTOCC#IK CPU Changi
24、ng Detect Pin 0: CPU present 1: CPU absent Table 5-6. Pin Description of Power/Ground Pin(s) No. Symbol Attribute Description 1 3VSB I Power Supply of 3.3V 16 GND I Ground 18 VBAT I Battery Power Supply of 3.3V Notes: IO cell types are described below: I: Input PAD IK: Schmitt Trigger Input PAD IO12
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