1、TMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.ATPG Introduction for IP Team TMFreescaleSemiconductorConfidentialand
2、ProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.AgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForS
3、canFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhatsit?DFTStructuredDFTATPGTerminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconduc
4、tor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.AgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhatsit?DFTStructuredDFTATPGTe
5、rminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleS
6、emiconductor,Inc.2006.Design Verification,Testing and DiagnosisDesignVerification:Besurethedesignperformitsspecifiedbehavior.Beforesilicon.Testing:Exercisethesystemandanalyzetheresponsetoascertainwhetheritbehavescorrectly.Aftersilicon.Diagnosis:Tolocatethecauseofmisbehavioraftertheincorrectbehaviori
7、sdetected.Aftersilicon.beforesiliconaftersiliconproductionengineeringTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.
8、Whats DFTDFT(DesignForTest)Testability isadesignattributethatmeasureshoweasyitistocreateaprogramtocomprehensivelytestamanufactureddesignsquality.Traditionally,designandtestprocesseswerekeptseparate,withtestconsideredonlyattheendofthedesigncycle.Butincontemporarydesignflows,testmergeswithdesignmuchea
9、rlierintheprocess,creatingwhatiscalledadesign-for-test(DFT)processflow.Testablecircuitryisbothcontrollable andobservable.Inatestabledesign;settingspecificvaluesontheprimaryinputsresultsinvaluesontheprimaryoutputswhichindicatewhetherornottheinternalcircuitryworksproperly.Toensuremaximumdesigntestabil
10、ity,designersmustemployspecialDFTtechniquesatspecificstagesinthedevelopmentprocess.TMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemicondu
11、ctor,Inc.2006.Whats Structured DFT?StructuredDFTProvidessystematicandautomaticapproachtoenhancingdesigntestability.Goalistoincreasethecontrollabilityandobservabilityofacircuit.Methods:scan designtechnique,whichmodifiestheinternalsequentialcircuitryofthedesign.Built-inSelf-Test(BIST)method,whichinser
12、tsadevicestestingfunctionwithinthedeviceitself.boundary scan,whichincreasesboardtestabilitybyaddingcircuitrytoachip.TMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirre
13、spectiveowners.FreescaleSemiconductor,Inc.2006.Whats ATPGATPG(AutomaticTestPatternGeneration)Testpatterns(testvectors),aresetsof1sand0splacedonprimaryinputpinsduringthemanufacturingtestprocesstodetermineifthechipisfunctioningproperly.ATE(AutomaticTestEquipment)determinesifthecircuitisfreefrommanufac
14、turingdefectsbycomparingthefault-freeoutputwhichisalsocontainedinthetestpatternwiththeactualoutputmeasuredbytheATE.Goal:createasetofpatternsthatachievesagiventestcoverage.ThenrunitonTester.Passindicatednorelateddefectsexistinthischip.TMFreescaleSemiconductorConfidentialandProprietaryInformation.Free
15、scaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.AgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksandde
16、liverablesScriptsandDemosQ&AWhatsit?DFTStructuredDFTATPGTerminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorse
17、rvicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.SCAN Cell/SCAN ChainScanCellInnormaloperation(sc_en=0),systemdatapassesthroughthemultiplexertotheDinputoftheflip-flop,andthentotheoutputQ.Inscanmode(sc_en=1),scaninputdata(sc_in)passestotheflip-flop,andthentothescanoutpu
18、t(sc_out).ScanChainAsetofseriallylinkedscancells.Eachscanchaincontainsanexternalinputpinandanexternaloutputpinthatprovideaccesstothescancells.Thescanchainlength(N)isthenumberofscancellswithinthescanchain.TMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretra
19、demarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.SCAN ProcedureTheoperatingprocedureofthescancircuitryisasfollows:1.Enablethescanoperationtoallowshifting(toinitializescancells).2.Afterloadingthescancells,holdthesca
20、nclocksoffandthenapplystimulustotheprimaryinputs.3.Measuretheoutputs.4.Pulsetheclocktocapturenewvaluesintoscancells.5.Enablethescanoperationtounloadandmeasurethecapturedvalueswhilesimultaneouslyloadinginnewvaluesviatheshiftingprocedure(asinstep1).BeforeScanAfterScanTMFreescaleSemiconductorConfidenti
21、alandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.SCAN Waveformscan_clkscan_seLoadshift shift shiftLoad/Unloadshift shift shiftcapturecaptureLoad/Unloadc
22、aptureLoad/UnloadcaptureUnloadTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.SCAN TypesFullScanHighlyautomatedproces
23、s.Highly-effective,predictablemethod.Easeofuse.Assuredquality.PartialScanReducedimpactonarea.Reducedimpactontiming.Moreflexibilitybetweenoverheadandfaultcoverage.Re-useofnon-scanmacros.TMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleS
24、emiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.Stuck-At Fault ModelExample:SingleStuck-AtFaultsforANDGateThesingle stuck-at modelisthemostcommonfaultmodelusedinfaultsimulation,becauseofitseffectivenessinfindingmanycommondefecttypes
25、Thestuck-atfaultmodelsthebehaviorthatoccursiftheterminalsofagatearestuckateitherahigh(stuckat-1)orlow(stuck-at-0)voltage.Thefaultsitesforthisfaultmodelincludethepinsofprimitiveinstances.Alls-a-0faultsintheANDgateareequivalents-a-1 s-a-0s-a-1s-a-0s-a-1 s-a-0s-a-0s-a-0s-a-1s-a-1s-a-0s-a-1Possible Err
26、ors:6Possible Errors:4TMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.Stuck-At Coverage Report#DT-TestCoverage=#FU-#U
27、U-#TI-#BL-#RE#DT-FaultCoverage=#FUStatisticsreport-#faults#faultsfaultclass(coll.)(total)-FU(full)1171003 1824936-UC(uncontrolled)3284UO(unobserved)9461286DS(det_simulation)35808011DI(det_implication)410(protected)11381701767804PU(posdet_untestable)7841806PT(posdet_testable)3442UU(unused)30355344TI(
28、tied)20932201BL(blocked)331333RE(redundant)827210462AU(atpg_untestable)13722 27553-test_coverage98.66%98.30%fault_coverage97.50%97.31%atpg_effectiveness99.91%99.92%-ProtectedFaultsalone:test_coverage98.35%97.85%fault_coverage97.20%96.87%-#test_patterns271#simulated_patterns271CPU_time(secs)18364.6-T
29、MFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.AgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContention
30、ClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhatsit?DFTStructuredDFTATPGTerminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescale
31、logoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.Combinational Loop&Tri-state ButCombinationalLoopNoticethattheA=1,B=0,C=1statecausesunknown(oscillatory)behavior,whichposesatestabilityproblem.Itshouldbeav
32、oidifpossible.Tri-stateBusContentionTri-stateBusisnotpermittedinsidechip.TMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2
33、006.Divided ClockSomedesignscontainuncontrollableclockcircuitry;thatis,internally-generatedsignalsthatcanclock,set,orresetflip-flops.Ifthesesignalsremainuncontrollable,theycoulddisturbsequentialelementsduringscanshifting.Thus,thesystemcannotconverttheseelementstoscan.new_clk=scan_mode?tst_clk:gen_cl
34、kTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.Async ResetTestLogicAddedtoControlAsynchronousResetuseipt_async_seto
35、controlthemux.new_rst=ipt_se_async_xxx?ext_rst:int_rstTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.Async Reset(2)F
36、orthecasewherebothsetandresetofaflopareinternallygenerated,eithersetorresetshallbedisabledduringscanmodeusingipt_mode_scansignal,whileothercanbemuxedwithhardresetusingipt_se_asyncsignal.Selectionofdisablingset/resetsignalshallbedecidedhavinglesscombinationallogicforgettingbettertestcoverage.TMFreesc
37、aleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.Clock GatingClockGatingWhenclkispulsedfromlowtohigh,thelatchisdisabledandrema
38、inssoaslongastheclksignalstayshigh.Therefore,eveniftheoutputofdff1changesfromhightolowasaresultoftheleadingedgeofthepulse,thatvaluechangecannotpropagatethroughthelatchandeffectclk_enuntilclkgoeslowagain,enablingthelatch.Equallyimportant,scanchainsmustoperatecorrectly.Youcanforceseto1intheload_unload
39、procedure;however,itmustbedonebeforeany“applyshift”statement.Thesesignalmustbecontrollableto1fromthechipsprimaryinputs(ICpins).InIPDFTguidethissesignalisconnectedtoipt_se_gatedclkp.TMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemic
40、onductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.Clock Gating(2)ClockGatingCellCPE+TEQDQTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductor
41、servicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.AgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhatsit?DFTStructuredDFTATPGTerminologyinScanScancellSc
42、anchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.DFT
43、 SignalsDFTsignalsIpt_mode_scan_xxxIpt_se_xxxIpt_se_async_xxxIpt_se_gatedclkn/p_xxxIpt_si/so_xxxIpt_dbg_tck_xxxIpt_dbg_trst_xxxIpt_dbg_tms_xxxIpt_dbf_tdi_xxxIpt_dbg_tdo_xxxPleaserefertoSection2.3ofTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarks
44、ofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.AgendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhatsit?D
45、FTStructuredDFTATPGTerminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespec
46、tiveowners.FreescaleSemiconductor,Inc.2006.Soft IP TasksPleaserefertoSection2.1.1ofTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemicondu
47、ctor,Inc.2006.Soft IP to SoC DeliverablesPleaserefertoSection2.1.2ofTMFreescaleSemiconductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.A
48、gendaDFTRulesCombinationalLoopAsynchronousResetTri-stateBusContentionClockDividersClockGatingDFTsignalsForScanFordebugSoftIPtasksanddeliverablesScriptsandDemosQ&AWhatsit?DFTStructuredDFTATPGTerminologyinScanScancellScanchainScanprocedureScanwaveformScantypeScanfaultmodelScanCoverageTMFreescaleSemico
49、nductorConfidentialandProprietaryInformation.FreescaleandtheFreescalelogoaretrademarksofFreescaleSemiconductor,Inc.Allotherproductorservicenamesarethepropertyoftheirrespectiveowners.FreescaleSemiconductor,Inc.2006.Coverage Collection Demo1.modifymodule.invokefilea.includethenetlistyouwanttorunfastsc
50、anb.changethetopname2.modifymodule_fs.dofilea.changeContrsintsA,B,C,Dforyourmodule3.modifymodule_fs.testproca.changethealiasforyourmodule4.modifychain_out.dofilea.addallthescanchainsofyourmodule5.Commandline:mkdir./output./module.invokeallthereportandlogfilewillbeputinthe./outputTMFreescaleSemicondu
