ASIC和FPGA架构的混合 电信专业英语论文.doc

A Hybrid ASIC and FPGA Architecture Applications Emerge for Hybrid Devices Implementation using an ASIC approach typically yields a faster, smaller, and lower power design than implementation in FPGA technology. The growing requirements in the marketplace for design flexibility however, are driving the need for hybrid ASIC/FPGA devices. The potential to change hardware configuration in real time, to support multiple design options with a single mask set, and to products usable life, all compel designers to look for a blending of high density ASIC circuits along with the inherent FPGA circuit flexibility. The ability to create a “base design” and then reuse the base with minimal changes for subsequent devices helps reduce design time and encourages standardization. Since many consumer and office products are offered with a range of low to high-end options, this base design concept can be effectively used - with features added to each successive model. Printers, fax machines, PC's and digital imaging equipment are examples where this concept can be useful. DSP applications are also well suited to FPGA because of the FPGAs fast multiply and accumulate (MAC) processing capability. When building a DSP system, the design can take advantage of parallel structures and arithmetic algorithms to minimize resources and exceed performance of single or multiple purpose DSP devices. DSP designers using both ASIC and FPGA within the same design can optimize a system for performance beyond the capabilities of either separate circuit technology. Other applications that lend themselves to the hybrid ASIC/FPGA approach are designs that support multiple standards such as USB, FireWire and CameraLink, in a single device. Similarly, designs that are finalized, with the exception of any undefined features or emerging standards , are excellent candidates for this technology. Without the benefit of programmable logic, the designer must decide between taping-out the chip knowing that the PCI logic has a high probability for change, or waiting until the design requirements are firm potentially impacting the end products schedule. With both programmable logic and ASIC working together on a single device, some situations like these can be accommodated. Other similar issues like differing geographic or I/O standards could also be incorporated within the FPGA cores, without requiring mask and fabrication updates for each change. Economics Play a Role in Using Hybrid Devices While technical applications are emerging for the hybrid architecture, it is unlikely that design teams would utilize this new capability unless it is also economically viable. We will now explore the economics behind this new architecture. To realize the performance and density advantages of an ASIC, design teams must accept higher NREs and longer TATs than FPGAs. Unlike off-the-shelf FPGAs, each ASIC design requires a custom set of masks for silicon fabrication. The custom mask set allows circuitry and interconnections to be tailored to the requirements of each unique application - yielding high performance and density. However, the cost of the mask sets is rapidly increasing (nearly doubling with each successive technology node). As a result, mask costs are becoming a significant portion of the per-die cost in many cases . For example, consider the case where a mask set costs $1,000,000. For applications where only 1,000 chips are required, each chip will cost well over $1000, since the mask cost (plus many other expenses) must be amortized over the volume of chips sold. As the volume requirements for this same ASIC rise, the effective cost of each die decreases. Conversely, FPGAs are standard products, where the mask charges for a small number of design passes are amortized over a large number of customers and chips, so the mask cost per chip sold is minimal. As a result, for each technology node there is a volume threshold, below which its more cost-effective to buy an FPGA chip vs. a smaller ASIC chip.TAT is another primary economic driver, having a direct impact on time -to-market for many applications. The time required for ASIC layout and fabrication is typically in the range 2-5 months - much longer than FPGAs, which generally require 1-4 weeks once a customers RTL is firm. These NRE and TAT issues are compounded by customers needs for multiple design passes. Since each ASIC design requires a unique mask set, if a customer discovers logic errors or needs to add features after tape out, they must initiate another ASIC design pass, requiring additional NRE charges and silicon fabrication time. As silicon technologies progress and chip designs become more complex, design verification becomes increasingly difficult, and the chance for logic errors grows. In many cases, time to market pressures drive design teams to continue verification well into layout and sometimes beyond chip tape out. This increases the risk that logic updates will be required, and therefore cost per chip will increase. In summary, ASICs to date have offered higher performance in smaller chip sizes than FPGAs. However, the NRE for current technology nodes has rendered them very expensive for applications that require low quantities of chips - particularly when multiple designs or design passes are required. The Hybrid ASIC/FPGA Solution Enter the hybrid ASIC/FPGA. Like an ASIC, the initial mask set must be purchased. But with the incorporation of FPGA cores into the ASIC, it is now possible to use the programmable circuitry to enable a single physical chip design to satisfy several different applications. This has the potential to eliminate multiple designs and in some cases, avoid costly respins. In the case where a customer requires several similar ASICs for a family of products, FPGA circuitry can be added to the base ASIC logic and be configured as needed to satisfy the multiple applications. Similarly, logic updates required to correct bugs discovered late in the verification process, or to accommodate changing market needs, can be handled with appropriately placed FPGA cores. The question must be asked; why embed FPGA into an ASIC if a two chip solution could achieve the same results? The answer is both technical and economic. Technically, for a certain class of applications, the embedded solution offers greater performance with lower power dissipation. By embedding the FPGA into the ASIC, signals that must propagate from the ASIC through the FPGA, then back to the ASIC can avoid four chip boundary delays, two card crossings, and the associated power dissipation. By keeping the ASIC to FPGA interconnections on the die, valuable ASIC I/O pins are also conserved. Economically, the embedded solution can be the less expensive option. As we will discuss, the FPGA fabric does not require any unique semiconductor processing above and beyond the base ASIC (unlike embedded flash or embedded DRAM). The resulting increase in ASIC cost is associated with the area occupied by the embedded FPGA core. In addition, the cost of assembly, test and packaging of a second chip are eliminated. In certain cases, it can be advantageous to include embedded FPGA on an ASIC if that FPGA eliminates the need for additional design passes. For example, at volumes of up to 250,000 pieces, 50K gates of embedded FPGA are cost effective. Similarly, 10K gates of embedded FPGA are cost effective versus a 2 pass ASIC design at volume of up to 1M. In general, if mask costs rise, volumes decrease, or more design passes are avoided, then the embedded FPGA approach becomes progressively more cost-effective compared to the ASIC approach. This is because at low volumes, the mask costs (and NRE) for additional design passes becomes a significant adder to per-chip cost, and this can outweigh the cost impact of the larger die area required by the embedded FPGA circuitry. This analysis leads us to conclude that technology and market trends have created a need for the development of the hybrid ASIC/FPGA product. Mask costs for advanced technologies are growing - making multiple design passes too costly for many applications. Fortunately, the technology advancements that have driven this trend have also opened up the potential to embed significant amounts of FPGA gates onto an ASIC die - enough to handle some of the design updates that would otherwise require additional design passes. Hybrid Offering Overview The IBM/Xilinx hybrid will first be available in IBMs Cu-08 90nm ASIC offering, and will consist of three FPGA block sizes. Multiple blocks can be used on the same die and the sizes of blocks used can be mixed and matched. Table 1 shows the features of the various blocks. Table 1 Hybrid offering Estimated Equivalent ASIC Gate Estimated Size Signal IO 10K 3 mm2 384 20K 5 mm2 512 40K 7 mm2 640 Physically, the FPGA cores are being ported to the same semiconductor process that the ASIC product uses . The issues encountered in doing this porting are similar to those of other 3rd party IP ports. One of the largest challenges is full chip physical verification. Common design rules and transistor design points are critical in blending of IP between suppliers. Minor differences in design rules can be accommodated, assuming that checking decks and other verification software are able to handle the mixture of design rules. Designing these tools for increased flexibility will likely be needed as more companies share IP. To ensure that the FPGA can be integrated with the rest of the ASIC, agreements must be reached on metal stack options. In the case of the Cu-08 hybrid offering, 5 levels of metal were allocated to the FPGA blocks. This requires a re-layout of the FPGA cores, which were originally designed for a standard product with 9 levels of metal. As part of the re-layout, the power distribution of the FPGA blocks will be designed to integrate easily into the ASIC power distribution methodology. Care needs to be taken to ensure the power density required by the FPGA blocks are within the capability of the ASIC power supply routing. Due to extensive use of pass-gate structures, the FPGA blocks require standard 1.2V power supply levels, and are not operable below 1.0 Volt. For low-power applications, the FPGA blocks will make use of IBMs Voltage Island capability, allowing them to operate at typical 1.2V levels, while the bulk of the chip operates at lower levels . The embedded FPGA blocks consist of programmable logic blocks, configuration logic, test interface logic, and simplified IO buffers for use in driving and receiving on-chip nets. Multiple end user configuration modes are supported including JTAG, serial and parallel modes. Individual cores can be configured asynchronously, allowing for “on-the-fly” reconfiguration. To design the new hybrid chips, a modified design methodology is being developed as shown in Figure 1. This hybrid design flow incorporates two proven design methodologies, the IBM ASIC flow and the XILINX FPGA flow, including several third party vendor synthesis options. The ASIC methodology integrates the embedded FPGA as a hard core with appropriate ASIC level models. The FPGA flow, including timing closure of the FPGA configuration, is done using XILINX tools. The designer has the choice of using constraints or detailed timing from the XILINX tool flow to close the ASIC timing at the FPGA core interfaces. If an FPGA configuration is known prior to the design of the ASIC, actual timing information can be passed to the ASIC tools from the FPGA tools. If the logic content of the embedded FPGA is unknown, the ASIC design can be completed using timing assertions and the embedded FPGA design can be completed later. If the embedded FPGA design is being reconfigured after the ASIC is in manufacturing, the final timing constraints from the completed ASIC can be passed to the FPGA tools for timing closure of the new FPGA design. ASIC Design ASIC RTL FPGA RTL ASIC FLOW FPGA FLOW ASIC MASK DATA Bitstream Constraints Final Constreains The logical design of the chip must be partitioned prior to final synthesis . The logic destined for an FPGA block is processed independently of the logic destined for ASIC logic. When multiple FPGA logic blocks are used, each must be designed and optimized independently. The ASIC physical design process treats the FPGA macro similarly to other large placeable objects, except for port assignment. During the initial ASIC design, the port assignment of each embedded FPGA block can be modified to accommodate floor planning or timing requirements. Once the final ASIC design is taped-out, the port assignments are fixed for subsequent FPGA configurations. The IBM ASIC methodology has been described in references, and the Xilinx FPGA methodology is described in reference . As to be expected, most of the issues in creating the hybrid methodology occur at the boundary between the two methodologies. The mechanics of the communications between the two systems can be accomplished by creating data translators, however, optimization between the two systems can be difficult, due to the significant architectural differences between traditional ASIC flows and traditional FPGA flows. Planning for future reconfiguration In addition to partitioning, designers will face several other challenges in using embedded FPGAs. The basic question of how many FPGA gates to include is fundamental. Not only must the FPGA be sized sufficiently for the initial application, but enough unused FPGA resources must be left to support future logic configurations. This is a critical design-planning consideration, since once the hybrid chip has been implemented in silicon, a second (costly) mask set is required if the FPGA capacity is insufficient to handle the future configurations. To prevent this unfortunate situation, the design team must anticipate the potential growth in the logic which is to be implemented in the FPGA, as well as correctly estimate the embedded FPGA utilization that can be achieved. In addition, because the interconnect between the embedded FPGA and the ASIC is fixed in the mask set, any future interconnect requirements must be accounted for during the initial ASIC design. These are difficult architectural and design planning challenges that will require enhanced CAD tools to help in the design of tomorrows hybrid SOCs. For optimization tools to effectively partition hybrid designs, they must be able to correctly model the area, power and performance capabilities of both ASIC and FPGA circuit architectures. Since the architectures are so different in these characteristics, tools that are capable of efficiently and quickly assessing these tradeoffs will be needed to help the designers choose the best logic partition and specific circuit options for each portion of the design. Floorplanning and Physical Design Once the initial design is partitioned, the next step is to plan the physical layout of the chip. The h