GMW-3089-2004.pdf

WORLWIDE ENGINEERING STANDARDS General Specification Electrical/Electronic GMW3089 GMLAN Single Wire CAN Physical and Data Link Layers Specification 1 Introduction 1.1 Scope. This document specifies the physical layer requirements for a Carrier Sense Multiple Access/Collision Resolution (CSMA/CR) data link which operates on a single wire medium to communicate among Electronic Control Units (ECU) on road vehicles at normal transmission rates of 33.333 Kbits/s and at a special high speed assembly or service transmission bit rate of 83.333 Kbits/s. This document is to be referenced by the particular Component Technical Specification which describes any given ECU in which the single wire data link controller and physical layer interface is located. Only the performance of the data link physical layer is specified in this document. ECU environmental and other requirements shall be provided in the Component Technical Specification. The intended audience includes, but is not limited to ECU suppliers, Controller Area Network (CAN) controller suppliers, CAN transceiver suppliers, component release engineers and platform system engineers. 1.2 Mission/Theme. This specification describes the physical layer requirements for a single wire data link capable of operating with various CSMA/CR protocols such as the Bosch Controller Area Network (CAN) version 2.0. This serial data link network is intended for use in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor and/or dedicated logic devices which use the network. The network shall be able to operate in either the normal data rate mode or a high speed data download mode for assembly line and service data transfer operations. The high speed mode is only intended to be operational when the bus is attached to an off-board service node. This node shall provide temporary bus electrical loads which facilitate higher speed operation. Such temporary loads shall be removed when not performing download operations. This physical layer specification includes such transceiver requirements as are necessary to insure that the bus voltage signals and that a common IC footprint can be achieved across all applications. The transceiver requirements are specified in Appendix C. 1.3 Classification. This specification is not restricted. 2 References Note: Only the latest approved standards are applicable unless otherwise specified. 2.1 External Standards/Specifications. ISO 11898 SAE #970295 ISO 16845 SAE J2411 2.2 GM Standards/Specifications. GM-J1962 GMW3103 GME6718 GMW3104 GMW3001 GMW3122 GMW3059 GMW3172 GMW3091 GMW3173 GMW3097 2.3 Additional References. Supplier Documents. The following devices have been approved for use. Any deviations to this spec have been noted. Melexis TH8056 contact Adrian Hill (248) 543-0682 for details. In Europe contact Michael Bender at +49-361-427-8355. Freescale (formerly Motorola SPS) MC33897*/R2 contact Deanna Waun (248) 347-7354 for details. In Europe contact Norbert Pickel at +49-6128-70-2975. This device cannot be used in vehicles implementing partial networks. This device does not meet the maximum recessive voltage when in Sleep Mode. The maximum recessive voltage of this device in sleep mode is 0.7V. This device shall not be used in new designs, it has been replaced by MC33897A*/R2. Freescale (formerly Motorola SPS) MC33897A*/R2 contact Deanna Waun (248) 347-7354 for details. In Europe contact Norbert Pickel at +49-6128-70-2975. This device will be designed to operate with partial networks © Copyright 2004 General Motors Corporation All Rights Reserved December 2004 Originating Department: North American Engineering Standards Page 1 of 37 GMW3089 GM WORLDWIDE ENGINEERING STANDARDS and will meet the specified maximum recessive voltage in sleep mode. The following devices are under development and are not approved for use to date. On Semiconductor NCV7356 contact Tom Bricely (734) 953-6848 for details. In Europe contact Klaus Reindl at +49-89-930808-32. The following supplier produced transceivers for version 1.26 of GMW3089. They are currently considering designing a device to these new requirements. Philips contact Dan Moore (248) 699-2264 for details The following supplier produced transceivers for version 1.26 of GMW3089. They currently have no plans to design a device to these new requirements Infineon contact Dario David (248) 374-2505 for details Other Documents - Bosch Controller Area Network version 2.0 specification (only with recessive to dominant bit synchronization). 3 Requirements The physical layer is responsible for providing a method of transferring digital data symbols (1s and 0s) to the communication medium. The physical layer interface is a single wire, ground referenced bus with high side voltage drive. Requirements in this document generally apply over the specified operating conditions and life time unless otherwise noted. 3.1 Physical and Data Link Layer Characteristics. a. Carrier Sense Multiple Access/Collision Resolution (CSMA/CR) bus access and arbitration with dominant high and recessive low signal voltages. b. Only performs bit re-synchronization on recessive to dominant bit transitions. c. The CAN controller shall be capable of transmitting and receiving messages with both standard frame format, i.e. 11 bit CAN identifiers, and extended frame format, i.e. 29 bit CAN identifiers (CAN 2.0B active). The CAN controller shall support mixed mode operation with CAN identifiers of both 29-bit and 11-bit in length. Alternatively tolerant of messages with extended frame format (CAN 2.0B passive) if explicitly called out per SSTS, CTS or platform-specific bus implementation specification. The CAN controller shall be fully compatible to ISO 11898. For example the enhanced protocol for higher clock tolerance must be supported (e.g. tolerate 2 bit message intermission). d. Compliance to ISO 11898 shall be verified through CAN conformance testing according to the ISO 16845 test plan. Successful passing of the complete conformance test shall be documented through provision of a written statement of the semiconductor manufacturer. The test plan conformance declaration shall indicate which product version was tested and which version of the CAN conformance test plan was used as reference. e. The controller must support the complete range of resynchronization jump width settings specified in ISO 11898. In particular, a bit timing parameter setting of SJW = 2 time quanta = PHASE_SEG2 must be supported. Also, the resynchronization function must be operational when a synchronization edge is detected outside the range set by the SJW parameter, i.e. when the phase error is greater than the SJW, the CAN controller shall adjust the timing of the current bit by SJW time quanta. f. The controller must perform at most one hard- and/or re-synchronization action per CAN bit time, the time between any two sample points. The earliest point in time when the next re-synchronization is permitted is after the sample point of the current bit as determined by the most recent bit resynchronization action. This means after any bit resynchronization action (hard- and/or re- sync) the resynchronization function must be disabled until the currently pending bit sampling has been concluded. This would allow the next resynchronization (at the earliest) in TSEG2 of this bit if the sample result was “recessive”. This case might occur due to a glitch on the bus. Note this requirement applies to both the hard- synchronization function at the start of a frame as well as to the re-synchronization function while frame transmission/reception is ongoing. g. When the bus is idle and a recessive to dominant signal edge has occurred then the controller shall behave in the following manner: 1. The controller must sample the bit value at the specified time after this signal edge and must disregard any consecutive edges until sampling of the current bit has been concluded (e.g. hard sync function must be © Copyright 2004 General Motors Corporation All Rights Reserved Page 2 of 37 December 2004 -,-,- GM WORLDWIDE ENGINEERING STANDARD GMW3089 disabled immediately upon receipt of the first r-d edge after an idle period). 2. If the sampling result is “dominant”, then this event shall be taken as a valid start of frame bit. 3. Otherwise, if the sampling result is “recessive”, then the edge shall be considered as a glitch and shall be disregarded. In particular, there must not be any error frame transmission due to a glitch while the bus is idle. h. It is not recommended to feed CAN controllers with a PLL-generated clock signal. If a CAN controller is operated with a PLL clock, then careful analysis of the implications of the additional clock jitter is required. As a preventive measure extra accuracy requirements on the oscillator clock apply in this case, see 3.2.4. i. The information processing time of the protocol controller must be equal to 2 time quanta or less. j. The CAN controller may employ a message buffer concept with or without Dual Ported RAM (DPRAM). k. The CAN protocol controller shall provide at least 2 transmit message buffers and 2 receive message buffers. This is to ensure that higher priority messages are not blocked by lower priority messages and that new messages are not dropped while the CPU is still reading the current message. l. Any time when more than one transmit buffer is armed for transmission, then the protocol controller shall automatically (e.g. without any CPU-support) transmit the message with the lowest CAN identifier first. m. When two or more messages with the same CAN identifier are armed for transmission, then the protocol controller shall transmit these messages in a FIFO fashion, i.e. in the sequence how they were armed. 3.2 Bus Operation. 3.2.1 Normal Communication. Transmission bit rate in normal communication is 33.333 Kbits/s. Normal transmission mode shall use transmitters with controlled waveform rise and overshoot times. Waveform trailing edge control is required to assure that high frequency components are minimized at the beginning of the downward voltage slope. The remaining fall time occurs after the bus is inactive with drivers off and is determined by the RC time constant of the total bus load. 3.2.1.1 CAN Controller Setup. The following table defines all compliant bit timing settings for operation at 33.333 kb/s including the recommended controller settings for TSEG1 and TSEG2. See appendix G for information on how these values were calculated. Table 1: 33.333 kb/s Compliant Bit Timing Settings tQ tSJW tSEG2min SJW TSEG1 TSEG2 1.5 µs 4.5 µs 4.5 µs 2 (3 tq) 15 (16 tq) 2 (3 tq) 1.58 µs 3.16 µs 3.16 µs 1 (2 tq) 15 (16 tq) 1 (2 tq) 1.67 µs 3.33 µs 3.33 µs 1 (2 tq) 14 (15 tq) 1 (2 tq) 1.76 µs 3.52 µs 3.52 µs 1 (2 tq) 13 (14 tq) 1 (2 tq) 1.88 µs 3.76 µs 3.76 µs 1 (2 tq) 12 (13 tq) 1 (2 tq) 2.0 µs 4.0 µs 4.0 µs 1 (2 tq) 11 (12 tq) 1 (2 tq) © Copyright 2004 General Motors Corporation All Rights Reserved December 2004 Page 3 of 37 GMW3089 GM WORLDWIDE ENGINEERING STANDARDS 3.2.2 High Speed Communication. Transmission bit rate in high speed communication is 83.333 Kbits/s. This mode is used for assembly line and service data download when the on-board network is attached to an off-board ECU. High speed transmission mode allows shortened bit time and shortened waveform rise and fall times. EMC requirements in 3.5 Radiated EMI protection are waived while in this mode. Bus transmitter drive circuits for those nodes which are required to communicate in high speed mode shall be able to drive reduced bus resistance when in this mode (see Table 1). High speed communications shall utilize the normal mode signal voltage levels as specified in Table 1. The test tool must connect Rtool to the bus before transmitting any high speed messages. Rtool shall be connected directly to ground on the ECU via an appropriate switch (e.g. transistor or relay). Rtool shall never be connected to the Load pin of the transceiver. The Load pin is not designed to handle the high level of current through Rtool. All nodes shall be able to operate at the High Speed mode frame timing and shall enter this mode when they have been commanded by the download system manager. The normal sequence of entering and leaving high speed mode is as follows, commanded by the download system manager (additional steps may be inserted by the download system manager as needed): a. All nodes are awakened at normal bus speed b. The download tool switches the bus circuit to the lower tool bus resistance c. All nodes are commanded to go to high speed mode d. High speed traffic is completed e. All nodes are commanded to go to normal speed mode f. The download tool switches the tool bus resistance out of the bus circuit Nodes shall not be allowed to go to sleep during high speed mode. If they are asleep and then get an input which would require them to send a message, they will corrupt the service activity. Nodes shall initialize in the normal speed mode after a power up, running reset or CAN bus off condition. 3.2.2.1 CAN Controller Setup. The following table defines all compliant bit timing settings for operation at 83.333 kb/s. Table 2: 83.333 kb/s Compliant Bit Timing Settings tQ tSJWmin tSEG2min SJW TSEG1 TSEG2 0.6 µs 1.8 µs 1.8 µs 2 (3 tq) 15 (16 tq) 2 (3 tq) 0.632 µs 1.896 µs 1.896 µs 2 (3 tq) 14 (15 tq) 2 (3 tq) 0.667 µs 2.0 2.0 µs 2 (3 tq) 13 (14 tq) 2 (3 tq) 0.706 µs 2.118 µs 2.118 µs 2 (3 tq) 12 (13 tq) 2 (3 tq) 0.75 µs 1.5 µs 2.25 µs 2 (3tq) 11 (12 tq) 2 (3 tq) 0.8 µs 1. 6 µs 1.6 µs 2 (3 tq) 10 (11 tq) 2 (3 tq) 0.857 µs 1.714 µs 1.714 µs 2 (3 tq) 9 (10 tq) 2 (3 tq) 0.923 µs 1.846 µs 1.846 µs 1 (2 tq) 9 (10 tq) 1 (2 tq) 1.0 µs 2.0 µs 2.0 µs 1 (2 tq) 8 (9 tq) 1 (2 tq) 3.2.3 ECU Selective Awake. This bus includes a selective node awake capability, which allows normal communication to take place among some nodes while leaving the other nodes in an undisturbed sleep state. This is accomplished by controlling the signal voltages such that all nodes must wake up when they receive a higher voltage message signal waveform. The communication system communicates to the nodes information as to which nodes are to stay operational (awake) and which nodes are to put themselves into a non communicating low power “sleep” state. Communication at the lower, normal voltage levels shall not disturb the sleeping nodes. The transceivers loss of ground protection circuit connection to ground shall not be interrupted when in the sleep mode. To accomplish this, all nodes shall maintain Vbatt on the transceiver at all times when any serial communication can take place. This is to ensure that the unit resistive loads shall © Copyright 2004 General Motors Corporation All Rights Reserved Page 4 of 37 December 2004 -,