IEEE-1076.3-1997.pdf

The Institute of Electrical and Electronics Engineers, Inc. 345 East 47th Street, New York, NY 10017-2394, USA Copyright © 1997 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 1997. Printed in the United States of America. ISBN 1-55937-923-5 No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. IEEE Std 1076.3-1997 IEEE Standard VHDL Synthesis Packages Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 20 March 1997 IEEE Standards Board Abstract: The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164- 1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arith- metic for arrays of common logic values. TwoÕs complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications. Keywords: interpretations, metalogical values, numeric VHDL vector types, signed, synthesis, un- signed Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/25/2007 02:58:31 MDTNo reproduction or networking permitted without license from IHS -,-,- IEEE Standards documents are developed within the IEEE Societies and the Standards Coordinat- ing Committees of the IEEE Standards Board. Members of the committees serve voluntarily and without compensation. They are not necessarily members of the Institute. The standards developed within IEEE represent a consensus of the broad expertise on the subject within the Institute as well as those activities outside of IEEE that have expressed an interest in participating in the develop- ment of the standard. Use of an IEEE Standard is wholly voluntary. The existence of an IEEE Standard does not imply that there are no other ways to produce, test, measure, purchase, market, or provide other goods and services related to the scope of the IEEE Standard. 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The IEEE shall not be responsible for identifying patents for which a license may be required by an IEEE standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention. Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/25/2007 02:58:31 MDTNo reproduction or networking permitted without license from IHS -,-,- iii Introduction (This introduction is not a part of IEEE Std 1076.3-1997, IEEE Standard VHDL Synthesis Packages.) This standard, IEEE Std 1076.3-1997, supports the synthesis and veriÞcation of hardware designs, by deÞn- ing vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. The standardization activity started during the development of IEEE Std 1076-1993, IEEE Standard VHDL Language Reference Manual, to address a number of issues in the synthesis area that could not be ade- quately addressed within the scope of the main 1076 project. The initial Synthesis Special Interest Group (SSIG) analyzed a wide range of requirements and grouped them in four categories: a)Standard Interpretations of IEEE Std 1164-1993 values for synthesis b)Numeric types for synthesis c)Special attribute semantics d)Constraint speciÞcation Consensus was reached only on solutions presented for categories a) and b). The large working group then commissioned a Pilot Team to drive the standardization effort. The three standardization chapters (North America, Europe, and Asia-PaciÞc) were all represented in the Pilot Team. The active members of the Pilot Team were the following: Alex N. ZamÞrescu, Chair The hard work and professionalism of the Pilot Team members contributed signiÞcantly to the Þnal result. Although the Working Group met regularly and voted on all major issues, the Pilot Team also extensively used electronic mail, a common repository, and several World Wide Web pages to accelerate the completely voluntary standardization process of the IEEE. A simple VHDL test suite (not part of the standard) that exer- cises and veriÞes the packages was also produced during standardization. A set of axioms and formal prop- erties involving standard operators has been formally proven. Wolfgang EckerEuropean Chapter Representative Kazuhiro YoshinagaAsia-PaciÞc Chapter Chair Rob AndersonLibrary Design Chair J. BhaskerBallot Comment Resolution Chair David BishopRepository and WWW Account Administrator Dominique BorrioneLeader, Formal VeriÞcation Effort James H. VellengaDocumentation and Pilot Team Co-Chair Rob Dekker Bob Flatt Chris Kingsley Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/25/2007 02:58:31 MDTNo reproduction or networking permitted without license from IHS -,-,- iv Individuals from many organizations participated in the development of IEEE Std 1076.3-1997. In addition to members of the Pilot Team, the following individuals attended meetings of the Synthesis Working Group: The following persons were on the balloting committee: Masamichi Kawarabayashi Chi Lai Huang Naotaka Maeda Sabine Maertz Kiyoshi Makino Yasunori Mako Erich Marschner Victor M. Martin Francoise Martinolle Michael McKinney Adam Morawiec Yutaka Murase Zainalabedin Navabi Kevin OÕBrien Dave Ackley Mart Altme Jean-Michel Berg Glenn Boysko Joanne DeGroat Allen Dewey Iain Finlay Bjrn Fjellborg Chris Flynn Brian GrifÞn Bradley Grove James P. Hanna John Hillawi Robert Hillman Masaharu Imai Venu Pemmaraju C. R. Ramesh Ray Ryan Larry F. Saunders Jay Schleicher Quentin Schmierer Kenneth E. Scott Manfred Selz Hirotake Shinde Dennis Soderberg Yuri Tatarnikov Victor Toporkov Tatiana Trondora Kerry Veenstra Eugenio Villar Mostapha Aboulhamid John Ainscough Robert E. Anderson LaNae Avra Pete Bakowski Daniel S. Barclay David L. Barton Mike Beaver Jean-Michel Berg Victor Berman J. Bhasker William D. Billowitch Dominique Borrione Dennis B. Brophy Walter H. Burkhardt Raul Camposano Todd P. Carpenter Moon Jung Chung David Coelho Edmond S. Cooley Alan Coppola Robert A. Cottrell Timothy R. Davis Allen Dewey Michael A. Dukes Douglas D. Dunlop William Fazakerly Robert A. Flatt Walter Geisselhardt Brian GrifÞn Richard Grisel Steve Grout Andrew Guyler James P. Hanna William A. Hanna Randolph E. Harr Frederick Hill Robert G. Hillman Kazuyuki Hirakawa Paul W. Horstmann Yee-Wing Hsieh Yu-I Hsieh Christophe Hui Bon Hoa Sylvie Hurat Masaharu Imai Mitsuaki Ishikawa Stephen Ives David Jakopac Takashi Kambe Masamichi Kawarabayashi Choon B. Kim Chris Kingsley Stanley J. Krolikoski Charles R. Lang Marc Laurent Jean Lebrun Steven Levitan Bob Lisanke Alfred Lowenstein Rajeev Madhavan Naotaka Maeda Serge Maginot Maqsoodul Mannan F. Erich Marschner Victor M. Martin Peter Marwedel Paul J. Menchini Jean Mermet Gerald T. Michael Israel Michel Toshio Misawa John T. Montague Larry Moore Gabe Moretti Vijay Nagasamy Zainalabedin Navabi Wolfgang W. Nebel Kevin OÕBrien Eamonn OÕBrien-Strain Yoichi Onishi Mauro Pipponzi Gary S. Porter Adam Postula Jean Pouilly Shiv Prakash Paolo Prinetto Jan Pukite Hemant G. Rotithor Jacques Rouillard Ray Ryan Johan Sandstrom Larry F. Saunders Quentin Schmierer Kenneth E. Scott Francesco Sforza Moe Shahdad Ravi Shankar Balmukund Sharma Charles Shelor Raj Singh Supreet Singh David W. Smith William Bong H. Soon Alec G. Stanculescu Balsha R. Stanisic Michael F. Sullivan Charles Swart Peter Trajmar Fatehy El-Turky Cary Ussery James H. Vellenga Ranganadha R. Vemuri Venkat V. Venkataraman Eugenio Villar Martin J. Walter Greg Ward Ronald Waxman Alan Whittaker John C. Willis Alex N. ZamÞrescu Reinhard Zippelius Mark Zwolinski Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/25/2007 02:58:31 MDTNo reproduction or networking permitted without license from IHS -,-,- v When the IEEE Standards Board approved this standard on 20 March 1997, it had the following membership: Donald C. Loughry, Chair Richard J. Holleman, Vice Chair Andrew G. Salem, Secretary *Member Emeritus Also included are the following nonvoting IEEE Standards Board liaisons: Satish K. Aggarwal Alan H. Cookson Kim Breitfelder IEEE Standards Project Editor Clyde R. Camp Stephen L. Diamond Harold E. Epstein Donald C. Fleckenstein Jay Forster* Thomas F. Garrity Donald N. Heirman Jim Isaak Ben C. Johnson Lowell Johnson Robert Kennelly E. G. ÒAlÓ Kiener Joseph L. KoepÞnger* Stephen R. Lambert Lawrence V. McCall L. Bruce McClung Marco W. Migliaro Louis-Franois Pau Gerald H. Peterson John W. Pope Jose R. Ramos Ronald H. Reimer Ingo Rsch John S. Ryan Chee Kiow Tan Howard L. Wolfman Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/25/2007 02:58:31 MDTNo reproduction or networking permitted without license from IHS -,-,- vi Contents 1.Overview 1 1.1 Scope 1 1.2 Terminology. 1 1.3 Conventions. 2 2.References 2 3.Definitions 2 4.Interpretation of the standard logic types. 3 4.1 The STD_LOGIC_1164 values.3 4.2 Static constant values. 4 4.3 Interpretation of logic values. 4 5.The STD_MATCH function 6 6.Signal edge detection. 6 7.Standard arithmetic packages 6 7.1 Allowable modifications 8 7.2 Compatibility with IEEE Std 1076-1987. 9 7.3 The package texts. 9 Annex A(informative) Notes on the package functions.39 A.1 General considerations. 39 A.2 Arithmetic operator functions 40 A.3 Relational operator functions. 41 A.4 Shift functions 42 A.5 Type conversion functions. 42 A.6 Logical operator functions. 43 A.7 The STD_MATCH function43 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/25/2007 02:58:31 MDTNo reproduction or networking permitted without license from IHS -,-,- 1 IEEE Standard VHDL Synthesis Packages 1. Overview 1.1 Scope This standard deÞnes standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following: a)The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE Std 1076-1993 1 and to the STD_ULOGIC type deÞned by IEEE Std 1164-1993. b)A function (STD_MATCH) that provides ÒdonÕt careÓ or Òwild cardÓ testing of values based on the STD_ULOGIC type. c)Standard functions for representing sensitivity to the edge of a signal. d)Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and that deÞne arithmetic, shift, and type conversion operations on those types. This standard is designed for use with IEEE Std 1076-1993. ModiÞcations that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2. 1.2 Terminology The word shall indicates mandatory requirements strictly to be followed in order to conform to the standard and from which no deviation is permitted ( shall equals is required to ). The word should is used to indicate that a certain course of action is preferred but not necessarily required; or that (in the negative form) a certain course of action is deprecated but not prohibited ( should equals is recommended that ). The word may indi- cates a course of action permissible within the limits of the standard ( may equals is permit