IEEE-61523-3-2004.pdf

INTERNATIONAL STANDARD IEC 61523-3 First edition 2004-09 IEEE 1497 Delay and power calculation standards Part 3: Standard Delay Format (SDF) for the electronic design process Reference number IEC 61523-3(E):2004 IEEE Std. 1497(E):2001 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- Publication numbering As from 1 January 1997 all IEC publications are issued with a designation in the 60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1. Consolidated editions The IEC is now publishing consolidated versions of its publications. For example, edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the base publication incorporating amendment 1 and the base publication incorporating amendments 1 and 2. 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Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- Delay and power calculation standards Part 3: Standard Delay Format (SDF) for the electronic design process INTERNATIONAL STANDARD IEC 61523-3 First edition 2004-09 IEEE 1497 Commission Electrotechnique Internationale International Electrotechnical Commission © IEEE 2004 Copyright - all rights reserved IEEE is a registered trademark in the U.S. Patent any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees. 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any equipment declared to be in conformity with an IEC Publication. 6) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC/IEEE 61523-3 has been processed through IEC technical committee 93: Design automation. The text of this standard is based on the following documents: IEEE Std FDIS Report on voting 1497 (2001) 93/191/FDIS 93/196/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives. The committee has decided that the contents of this publication will remain unchanged until 2006. IEC 61523 consists of the following parts, under the general title Delay and power calculation standards: IEC 61523-1, Part 1: Integrated circuit delay and power calculation systems Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved. IEC 61523-3:2004(E) IEEE 1497-2001(E) 3 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- IEC 61523-2, Part 2: Pre-layout delay calculation specification of CMOS ASIC libraries IEC/IEEE 61523-3, Part 3: Standard Delay Format (SDF) for the electronic process Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved. IEC 61523-3:2004(E) IEEE 1497-2001(E) 4 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- IEC/IEEE Dual Logo International Standards This Dual Logo International Standard is the result of an agreement between the IEC and the Institute of Electrical and Electronics Engineers, Inc. (IEEE). The original IEEE Standard was submitted to the IEC for consideration under the agreement, and the resulting IEC/IEEE Dual Logo International Standard has been published in accordance with the ISO/IEC Directives. IEEE Standards documents are developed within the IEEE Societies and the Standards Coordinating Committees of the IEEE Standards Association (IEEE-SA) Standards Board. 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Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 5 December 2001 IEEE-SA Standards Board Abstract: The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the formats contents will find it useful. Keywords: computer, computer languages, delay, delay backannotation, digital systems, electron- ic systems, hardware, hardware design, SDF, timing, timing analysis, timing backannotation, timing verification Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved. IEC 61523-3:2004(E) IEEE 1497-2001(E) 6 Copyright The Institute of Electrical and Electronics Engineers, Inc. Provided by IHS under license with IEEELicensee=NASA Technical Standards 1/9972545001 Not for Resale, 04/21/2007 11:47:33 MDTNo reproduction or networking permitted without license from IHS -,-,- Copyright © 2001 IEEE. All rights reserved. iii The Standard Delay Format (SDF) was designed to serve as a simple textual medium for communicating timing information and constraints between EDA tools. The original version was designed by Rajit C. Chan- dra in 1990 while at Cadence Design Systems, and was intended as a means of communicating macrocell and interconnect delays from Gate Ensemble to Verilog-XL, Veritime and other stand-alone tools requiring timing data. Because it was originally targeted for annotation to tools using the Verilog language, many SDF constructs are analogous to those in Verilog specify blocks. Those already familiar with the Verilog specify block will fi nd many of the SDF constructs familiar, such as SETUP and PATHPULSE. SDF also includes constructs for annotating interconnect delays, and can be used for forward annotation by specifying path del