基于AT89C51的遥控定时器外文翻译.doc

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1、毕业论文(设计)文献翻译本翻译源自于： CNKI数字图书馆 毕业设计名称：基于单片机的无线定时计时系统接口设计外文翻译名称： 基于单片机的定时器设计 学 生 姓 名 ： 魏巍 院 (系)： 电子信息学院 专 业 班 级 ： 电气10703班 指 导 教 师 ： 高秀娥 辅 导 教 师 ： 高秀娥 时 间 ： 2011年2月21日 至 2011年4月20日 基于AT89C51的遥控定时器电气10703班魏巍译描述：AT89C51是一个低电压，高性能CMOS 8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS

2、51系列的单片机兼容。片内含有8位中央处理器和闪烁存储单元，有较强的功能的AT89C51单片机能够被应用到控制领域中。功能特性：AT89C51提供以下的功能标准：4K字节闪烁存储器，128字节随机存取数据存储器，32个I/O口，2个16位定时/计数器，1个5向量两级中断结构，1个串行通信口，片内震荡器和时钟电路。另外，AT89C51还可以进行0HZ的静态逻辑操作，并支持两种软件的节电模式。闲散方式停止中央处理器的工作，能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。掉电方式保存随机存取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。引脚描述

3、VCC：电源电压 GND：地P0口：P0口是一组8位漏极开路双向I/O口，即地址/数据总线复用口。作为输出口时，每一个管脚都能够驱动8个TTL电路。当“1”被写入P0口时，每个管脚都能够作为高阻抗输入端。P0口还能够在访问外部数据存储器或程序存储器时，转换地址和数据总线复用，并在这时激活内部的上拉电阻。P0口在闪烁编程时，P0口接收指令，在程序校验时，输出指令，需要接电阻。P1口：P1口一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动4个TTL电路。对端口写“1”，通过内部的电阻把端口拉到高电平，此时可作为输入口。因为内部有电阻，某个引脚被外部信号拉低时输出一个电流。闪烁编程时和

4、程序校验时，P1口接收低8位地址。P2口：P2口是一个内部带有上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动4个TTL电路。对端口写“1”，通过内部的电阻把端口拉到高电平，此时，可作为输入口。因为内部有电阻，某个引脚被外部信号拉低时会输出一个电流。在访问外部程序存储器或16位地址的外部数据存储器时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器时，P2口线上的内容在整个运行期间不变。闪烁编程或校验时，P2口接收高位地址和其它控制信号。P3口：P3口是一组带有内部电阻的8位双向I/O口，P3口输出缓冲故可驱动4个TTL电路。对P3口写如“1”时，它们被内部电阻拉到高电平并可作为输入

5、端时，被外部拉低的P3口将用电阻输出电流。P3口除了作为一般的I/O口外，更重要的用途是它的第二功能，如下表所示：端口引脚第二功能P3.0RXDP3.1TXDP3.2INT0P3.3INT1P3.4T0P3.5T1P3.6WRP3.7RDP3口还接收一些用于闪烁存储器编程和程序校验的控制信号。RST：复位输入。当震荡器工作时，RET引脚出现两个机器周期以上的高电平将使单片机复位。ALE/PROG:当访问外部程序存储器或数据存储器时，ALE输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE以时钟震荡频率的1/16输出固定的正脉冲信号，因此它可对输出时钟或用于定时目的。要注意的是：每当

6、访问外部数据存储器时将跳过一个ALE脉冲时，闪烁存储器编程时，这个引脚还用于输入编程脉冲。如果必要，可对特殊寄存器区中的8EH单元的D0位置禁止ALE操作。这个位置后只有一条MOVX和MOVC指令ALE才会被应用。此外，这个引脚会微弱拉高，单片机执行外部程序时，应设置ALE无效。PSEN：程序储存允许输出是外部程序存储器的读选通信号，当AT89C51由外部程序存储器读取指令时，每个机器周期两次PSEN 有效，即输出两个脉冲。在此期间，当访问外部数据存储器时，这两次有效的PSEN 信号不出现。EA/VPP：外部访问允许。欲使中央处理器仅访问外部程序存储器，EA端必须保持低电平。需要注意的是：如果

7、加密位LBI被编程，复位时内部会锁存EA端状态。如EA端为高电平，CPU则执行内部程序存储器中的指令。闪烁存储器编程时，该引脚加上+12V的编程允许电压VPP，当然这必须是该器件是使用12V编程电压VPP。XTAL1：震荡器反相放大器及内部时钟发生器的输入端。XTAL2：震荡器反相放大器的输出端。掉电和空闲模式下的WDT：掉电时期，晶体振荡停止，看门狗定时器也停止。掉电模式下，用户不嗯那个在复位看门狗定时器。有两种方法可以推出掉电模式：硬件复位或通过激活外部中断，当硬件复位退出掉电模式时，处理看门狗定时器可像通常的上电复位一样。当由中断退出掉电模式时则有所不同，中断低电平状态持续到晶体振荡稳定

8、当中断电平变为高电平事即可相应中断服务。以防止中断误复位，当器件复位，中断引脚持续为低时，看门狗定时器并未开始计数，知道中断引脚被拉高时为止。这为在掉电模式下的中断执行中断服务程序而设置。为保证看门狗定时器在退出掉电模式时极端情况下不溢出，最好在进入掉电模式前复位看门狗定时器。在进入空闲模式前，看门狗定时器打开时，WDT是否继续计数由SFR中的AUXR的WDIDLE位决定，在IDLE期间（位WDIDLE=0）默认状态是继续计数。为防止AT89S51从空闲模式中复位，用户应该周期性地设置定时器，重新进入空闲模式。当WDIDLE位被置位，在空闲模式中看门狗定时器将停止计数，直到从空闲(IDLE)

9、模式中退出重新开始计数。中断：AT89S51共有五个中断向量：两个外部中断（ INT0和INT1 ） ，两个定时器中断（Timer0和Timer1)和一个串行中断。这些中断源各自的禁止和使能位参见特殊功能寄存器的IE。IE也包含总中断控制位EA，EA清0，将关闭所中断。空闲模式：在空闲工作模式状态， CPU保持睡眠状态而所有片内的外设仍然保持激活状态，这种方式由软件产生。此时，片内RAM和所有特殊功能寄存器的内特那个保持不变，空闲模式可由任何语序中断的请求或硬件复位终止。需要注意的是，当由硬件复位来终止空闲工作模式时，CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部

10、复位操作，硬件复位脉冲要保持两个机器周期有效，在这种情况下，内部禁止CPU访问片内RAM,而允许访问其他端口。为了避免在复位结束时可能对端口产生意外写入，激活空闲模式的那条指令的后一条指令不应该是一条对端口或外部存储器的写入指令。掉电模式： 在掉线模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉电模式的方法是硬件复位或由处于使能状态的外中断INT0和INT1激活。复位后将重新定义全部特殊功能寄存器，但不改变原来RAM中的内容，在VCC恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。模

11、式程序存储区ALEPSENPORT0PORT1PORT2PORT3空闲模式内部11数据数据数据数据空闲模式外部11浮空数据地址数据掉电模式内部00数据数据数据数据掉电模式外部00浮空数据数据数据表8-1 空闲和掉电期间外部引脚状态时钟震荡器：AT89C51中有一个用于构成内部震荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自然震荡器。 外接石英晶体及电容C1，C2接在放大器的反馈回路中构成并联震荡电路。对外接电容C1，C2虽然没有十分严格的要求，但电容容量的大小会轻微影响震荡频率的高低、震荡器工作的稳

12、定性、起振的难易程序及温度稳定性。如果使用石英晶体，我们推荐电容使用30PF10PF，而如果使用陶瓷振荡器建议选择40PF10PF。用户也可以采用外部时钟。采用外部时钟的电路如图示。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空。由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术条件的要求。11内部振荡电路 外部振荡电路定时器：8位的倒计数器（地址0FH）由定时器控制寄存器（地址0EH，参见表25）控制，定时器控制寄存器用于设定定时器的频率（4096，

13、64，1，或1/60Hz），以及设定定时器有效或无效。定时器从软件设置的8位二进制数倒计数，每次倒计数结束，定时器设置标志位TF（参见表7），定时器标志位TF只可以用软件清除，TF用于产生一个中断（/INT），每个倒计数周期产生一个脉冲作为中断信号。TI/TP控制中断产生的条件。当读定时器时，返回当前倒计数的数值。CLKOUT时钟输出：管脚CLKOUT可以输出可编程的方波。CLKOUT频率寄存器，决定方波的频率，CLKOUT可以输出32.768KHz(缺省值)，1024，32，1Hz的方波。CLKOUT为开漏输出管脚，通电时有效，无效时为高阻抗。石英晶片频：方法：定值OSCI电容计算所需的电容

14、平均值，用此值的定值电容，通电后在CLKOUT管脚上测出的频率应为32.768kHz，测出的频率值偏差去取决于石英晶片，电容偏差和器件之间的偏差（平均为510-6）。平均偏差可达5分钟年方法：OSCI微调电容可通过调整OSCI管脚的微调电容使振荡器频率达到精确值，这时可测出通电时管脚CLKOUT上的32.768kHz信号。方法3：OSCI输出直接测量管脚OSCI的输出。Design of AT89C51 Special-Purpose TimerDescription： The AT89C51 is a low-power, high-performance CMOS 8-bit microc

15、omputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be repr

16、ogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function charact

17、eristic：The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with sta

18、tic logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator

19、disabling all other chip functions until the next hardware reset.Pin Description：VCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedanc

20、e inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. Externa

21、l pullups are required during programverification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Por

22、t 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sin

23、k/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches

24、from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Po

25、rt 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high

26、by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Fla

27、sh programming and verification.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse inpu

28、t (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be

29、disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe

30、 to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enabl

31、e the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable

32、voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.WDT DURING Power-down and IdleIn Power-down mode the oscillator stops, whi

33、ch means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hard

34、ware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prev

35、ent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a f

36、ew states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state.

37、 To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.5.InterruptsThe

38、 AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 6-1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing

39、a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the sp

40、ecial function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles bef

41、ore the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one t

42、hat invokes idle mode should not write to a port pin or to external memory.Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Pow

43、er-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal ope

44、rating level and must be held active long enough to allow the oscillator to restart and stabilize.ModeProgram MemoryALEPSENPORT0PORT1PORT2PORT3IdleInternal 1 1DataDataDataDataIdleExternal 1 1FloatDataAddressDataPower-downInternal 0 0DataDataDataDataPower-downExternal 0 0FloatDataDataDataTable Status

45、 of External Pins During Idle and Power-down ModesOscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To dri

46、ve the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and

47、maximum voltage high and low time specifications must be observed. Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationTimer8 counters but actually (address 0FH) by the timer control register (address 0EH, see also Table 25) to control, decides when the control register uses in establishing timers frequency (4096,64,1, either 1/60Hz), as well as hypothesis timer effective or inv