先进芯片封装知识介绍.pptx

《先进芯片封装知识介绍.pptx》由会员分享，可在线阅读，更多相关《先进芯片封装知识介绍.pptx（34页珍藏版）》请在三一文库上搜索。

1、AdvancedPackagingTechAdvancedPackagingTechOutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackagePackageDevelopmentTrendSOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrendCSPFamilyMemoryCardSiPModulePackageDevelopmentTrend3DPackage3DPackage3DPackageIntroductionetCSPStackFunctionalIntegrationHighL

2、owTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP 3S-CSPS-etCSPetCSP+S-CSP PS-fcCSP+SCSP PoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP 5SCSPSS-SCSP(past

3、e)UltrathinStackD2D3D4D2D2D3D4D2 PoPQFN4SS-SCSPStackedDieTopdieBottomdieFOWmaterilWireTSVTSV(ThroughSiliconVia)Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.A3Dpackage(Systemi

4、nPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace.Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips.Insome

5、new3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSVWhatsPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.PoPPoPPS-vfBGAPS-etCSPLowLoo

6、pWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnologyPoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,w

7、irebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkorsTMVPoPTop viewBottom viewThrough Mold ViaPoPBallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseMtlThermaleffectProcessFlowofTMVPo

8、PDigital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiPEasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthass

9、tandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?PiPMaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTopPackageAttachDieAttachetcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISMPiPCoreTec

10、hnologyPiPMemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiPPiPW/BPiPandFCPiPWLCSP&FlipChipPackageWLCSPWhatisWLCSP?WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedt

11、odiesize).WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.WLCSPWhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinm

12、obiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSPsdisadvantageBecauseofthediesizeandpinpitchlim

13、itation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.RDLRDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafersactivesurfacetore-routethebondpads.Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).WLCSPProcessFlowofWLCSPW

14、LCSPProcessFlowofWLCSPFlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-FCBGA(Multi-Chip-ModuleFCBGA)PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMultiPackageFlipChi

15、p)BumpBumpDevelopmentBumpDevelopmentBumpDevelopmentC4FlipChipWhatsC4FlipChip?C4is:ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype:solder,goldC4FlipChipBGAMainFeaturesBallPitch:0.4mm-1.27mmPackagesize:upto55mmx55mmSubstratelayer:4-16LayersBallCount:upto2912Targ

16、etMarket:CPU、FPGA、Processor、Chipset、Memory、Router、Switches、andDSPetc.MainBenefitsReducedSignalInductanceReducedPower/GroundInductanceHigherSignalDensityDieShrink&ReducedPackageFootprintHighSpeedandHighthermalsupportC2FlipChipWhatsC2FlipChip?C2is:ChipConnectionChipisconnectedtosubstratebycopperpostBumpmaterialtype:copperpostwithsolderplatingSiliconDieCopperpostSolderC2FlipChipProcessFlowofC2C2FlipChipComparison:C2VsC4Insomecases,C2canreplaceC4orwirebondingpackage.Thanks!