机械专业外文文献翻译外文翻译AT89C52单片机.doc

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1、The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8 Kbytesof Flash programmable and erasable read only memory (PEROM). The device is manufac-tured using Atmels high density nonvolatile memory technology and is compatible with theindustry standard 80C51 and 80C52 instruction

2、set and pinout. The on-chip Flash allows theprogram memory to be reprogrammed in-system or by a conventional nonvolatile memoryprogrammer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the AtmelAT89C52 is a powerful microcomputer which provides a highly flexible and cost effect

3、ivesolution to many embedded control applications.The AT89C52 provides the following standard features: 8 Kbytes of Flash, 256 bytes ofRAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, afull duplex serial port, on-chip oscillator, and clock circuitry. In

4、addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/count-ers, serial port, and interrupt system to continue functioning. The Power Down Mode saves

5、the RAM contents but freezes the oscillator, disabling all other chip functions until the next hard-ware reset. A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be i

6、mplemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea-tures. In that case, the reset

7、or inactive values of the new bits willalways be 0. Control and status bits are contained in reg-isters T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.The individual interrupt enable bits

8、are in the IE register. Two priorities can be set for each of the six inter-rupt sources in the IP register.The AT89C52 implements 256 bytes of on-chip RAM. The up-per 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses

9、as the SFR space but are physically separate from SFR space.When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR

10、 space.For example, the following direct addressing instruction ac-cesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses th

11、e data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1

12、 in the AT89C51.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down count-ing), and baud rate generator.

13、 The modes are selected by bits in T2CON, as shown in Table 3.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

14、In the Counter function, the register is incremented in response to a l-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cy-cle and a low in the next cycle, the count i

15、s incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recog-nize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To

16、ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T

17、2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 per-forms the same operation, but a l-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be cap-tured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes b

18、it EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 1.Auto-Reload (Up or Down Counter)Timer 2 can be programmed to count up or down when config-ured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter

19、Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two

20、 options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in RCAP2H and RCAP2L are preset by software. If EXEN2 = 1

21、 a 16-bit reload can be triggered either by an overflow or by a l-to-0 transition at exter-nal input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this

22、mode, the T2EX pin controls the di-rection of the count. A logic 1 at T2EX makes Timer 2 count up.The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.A logic 0 at T2E

23、X makes Timer 2 count down. The timer under-flows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers.The EXF2 bit toggles whenever Timer 2 overflows or under-flows and can be used as a 17th bit of re

24、solution. In this operat-ing mode, EXF2 does not flag an interrupt.Baud Rate GeneratorTimer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter a

25、nd Timer 1 is used for the other function.Setting RCLK and/or TCLK puts Timer 2 into its baud rate gen-erator mode, as shown in Figure 4.The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be re-loaded with the 16-bit value in re

26、gisters RCAP2H and RCAP2L,which are preset by software.The Timer can be configured for either timer or counter opera-tion. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a tim

27、er, it incre-ments every machine cycle (at 1/12 the oscillator frequency). Asa baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). Timer 2 as a baud rate generator is shown in Figure 4. This fig-ure is valid only if RCLK or TCLK = 1 in T2CON. Note that a r

28、ollover in TH2 does not set TF2 and will not generate an inter-rupt. Note too, that if EXEN2 is set, a l-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H,RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external i

29、nterrupt.Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be rea

30、d but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.Programmable Clock OutA 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figu

31、re 5. This pin, besides being a regular I/0 pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16MHz operating frequency.To configure the Timer/Counter 2 as a clock generator, bit

32、 C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H,RCAP2L).In the clock-out mode, Timer 2 roll-overs will not generate a

33、n interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be deter-mined independently from one another since

34、they both use RCAP2H and RCAP2L.UARTThe UART in the AT89C52 operates the same way as the UART in the AT89C51.InterruptsThe AT89C52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1,and 2), and the serial port interrupt. These interrupt

35、s are all shown in Figure 6.Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Note that Table 5 shows that bit position IE.6 is unimple

36、mented. In the AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products.Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hard

37、ware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software.The Timer 0 and Timer 1 flags, TF0 and TFI, are set at S5P2 of the cycle in which the timers over

38、flow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be con

39、figured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or ce-ramic resonator may be used. To drive the device from an exter-nal clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 8. There are no require-ments on the duty cycle of

40、 the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.

41、The mode is invoked by software.The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.Note that when idle mode is terminated by a hardware reset, the device normally re

42、sumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin

43、when idle mode is terminated by a reset, the instruction follow-ing the one that invokes idle mode should not write to a port pin or to external memoryPower Down ModeIn the power down mode, the oscillator is stopped, and the in-struction that invokes power down is the last instruction exe-cuted. The

44、 on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating l

45、evel and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsThe AT89C52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain some additional features.When lock bit 1 is programmed, the logic level at the EA pin

46、 is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the de-vice to function properly.Programm

47、ing the FlashThe AT89C52 is normally shipped with the on-chip Flash mem-ory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either ahigh-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low voltage programming mode

48、provides a conven-ient way to program the AT89C52 inside the users system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C52 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-si

49、de marking and device signature codes.Programming Algorithm: To program the AT89C52, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12 V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is sel